The recent Embedded Systems Conference in San Jose, Calif., was primarily aimed at software developers. But chip designers should start paying more attention to this event and the technology it represents. In the coming era of systems-on-silicon, hardware and software design cannot take place in isolation, but must be coordinated using new tools and methodologies.
A class on software development for systems-on-silicon, taught by Jeff Payne and Arnie Berger of Applied Microsystems Corp., illustrated many new challenges that both hardware and software designers will face. One problem is that prototypes will come in later, lengthening the gap during which software designers can't move ahead without hardware. Another is that the hardware that does appear-in the form of a manufactured ASIC-will be much harder to work with or modify than a board-level target system.
An embedded processor core doesn't provide a way to hook up a traditional in-circuit emulator. If there's a JTAG port, you can probably hook up a debugging tool that provides some, but not all, of the features of an emulator. Visibility and control will be serious problems unless they're designed in from the beginning.
Hardware/software coverification tools can make things easier. These tools couple a software debugging environment with fast processor models and HDL simulation, so that VHDL or Verilog models represent prototype hardware that hasn't been built yet. This allows some early debugging, though HDL models run vastly more slowly than real hardware.
At the conference, Cadence Design Systems announced its entry into the coverification market, and Mentor, Synopsys and Summit displayed their latest products. Gaio Technology, a Japanese vendor, showed a coverification tool it will sell in the United States through Orion Instruments.
What's ultimately needed, however, is hardware/software codesign. Coverification takes place long after partitioning; codesign is system-level design before and during hardware/software partitioning. DSP codesign tools have been available for years, but more general-purpose tools are just now starting to appear.
As Cadence announced some details about its Felix codesign project, Arexsys, a French codesign startup, announced an interface with CS Verilog, a French computer-aided systems design company. And startup CoWare displayed its wares.
System-on-a-chip design is so new we haven't even defined all the problems yet. But the Embedded Systems Conference is a good place to look for some answers.
