Program Agenda
Presenter: Mike Muller, Chief Technology Officer, ARM Thanks to advances in semiconductor technology, consumer electronics have evolved to the point where we have pervasive mobile interaction via the Internet. However, despite process scaling down to 11 nm, fixed power budgets may soon make it impossible to utilize all the available transistors on a chip. Without fresh innovations, designers could find themselves at some point in an era of "dark silicon," able to build dense devices they cannot afford to power. In his keynote Muller will explain what needs to be done to light up this dark silicon and enable another generation of product innovation as well as ARM’s product and research roadmaps to enable this brighter future. |
Event Keynote: Dark Silicon and the Internet
About the Speaker: Mike Muller was one of the founding members of ARM back in 1990 when he occupied the post of Marketing Director. He switched roles in 1996 to become the executive VP of Business Development before taking over as CTO in 2000. Prior to ARM, Muller worked for Acorn as a principal engineer, responsible for product strategy for I/O and MMU architectures. He holds an MA in Computer Science from Cambridge University.
Moderator: John Donovan, Editor/Publisher, Low-Power Design
ARM’s focus on energy-efficient design has made it the dominant processor for mobile handsets. But new processor-intensive applications such as high-definition video are pushing current SoC energy efficiency strategies to the limit. This session will examine the current state of the art in power management and some new directions it needs to take. In a field as critical and fast moving as low-power design, there are numerous strategic options and more than a few speed bumps and dead ends. Our panel of experts will spell them out and detail how to implement a low-power design flow, working from the system level down a silicon-and/or board-level implementation.
Moderator: John Donovan, Editor/Publisher, Low-Power Design
Panelists: Brian Carlson (OMAP Platform Marketing Manager, Wireless Business Unit, Texas Instruments), Pete Hardee (Solutions Marketing Director, Cadence), Rick Zarr (PowerWise Technologist, National Semiconductor), Cary Chin (Director, Technical Marketing, Low Power Solutions, Synopsys, Inc.)
ARM has long been as dominant in the mobile handset market as Intel is in PCs. With the launch of Atom, Intel is trying to eat ARM's lunch in portable consumer electronics, even though ARM claims that its entry is far more power efficient than Intel's. Is the Cortex-A8 an Atom smasher?
Moderator: John Donovan, Editor/Publisher, Low-Power Design
While chip design speeds along following Moore’s Law, software development often seems to follow Murphy’s Law. It’s a lot easier to design multicore chips than it is to write code that can manage them—or to create compilers, debuggers and profilers that deliver small, fast executables. And if your RTOS doesn’t have hooks into the neat new features of your chosen chip, your 32-bit RISC CPU may perform like an 8-bit MCU. This session will focus on the software and tools you’ll need to create leading-edge ARM-based designs; it will also examine just what the latest RTOSs can and can’t do for your application. Our panelists will spend a good deal of time on test and debug issues, which is where embedded developers spend much of their time, too.
Moderator: Rich Nass, Editorial Director, UBM Electronics
Panelists:John Carbone (Vice President of Marketing, ExpressLogic), David Kleidermacher (Chief Technology Officer, Green Hills Software), Stephen Olsen (Software Architect, Embedded Systems Division, Mentor Graphics), Marc Serughetti (Vice President Marketing and Business Development, CoWare)
Ready or not, SOI technology is here and it is here to stay. Today, chip designers are able to realize power savings of 30% or more on SOI compared to traditional bulk silicon for the same or better performance. Discover the vitality of SOI technology in today’s designs and interact with Cadence and the SOI Consortium further about available SOI-based IP and design services.
Moderators: Susan Runowicz-Smith (Group Marketing Director, Cadence), Horacio Mendez (Executive Director, SOI Industry Consortium), Remy Pottier (Sr. Director, SOI Marketing and Business Development, ARM LTD), Gorden Starkey (Systems & Technology Group, IBM)
As the number of cores and frequency continue to increase, simple multi-layer AHB bus structures are becoming challenging and complex—making it nearly impossible to rapidly and cost-effectively design tomorrow’s embedded SoCs. Throughout most design cycles, memory access problems begin to emerge for latency-sensitive cores as multiple cores are now competing for memory. In this webinar, Sonics will address the challenges of designing embedded SoCs with multiple IP blocks and show SoC designers how to solve even the most complex on-chip connectivity problems. The presenter will discuss the most effective approach for combining new and legacy cores, simplifying your on-chip bus designs, and optimizing the performance of your AMBA-based SoC designs for next-generation applications such as wireless, home networking and automotive.
Presenter: Steve Hamilton, Senior Architect, Sonics, Inc.
About the speaker: Steve Hamilton has more than 30 years experience in the computer and semiconductor industries. His background includes chip-level development of both ASICs and custom ICs—including analog design—but also significant CAD software development expertise spanning logic simulation, place and route tools, and silicon compilation. For the past 10 years, Hamilton has been on the leading edge of the SoC revolution. Today, he serves as a Senior Architect for Sonics, addressing the unique challenges of SoC integration through on-chip network IP, specializing in handheld systems. Previously, Hamilton was the Chief IP Architect for a small company offering video and serial interface IP cores.
Lots of vendors offer ARM-based microprocessors. How, as a designer, do you decide which one is right for your application? We'll address that issue by looking at the various cores and the different vendors that produce processors based on those cores. And hopefully we can sort out which is best for your application.
Moderator: Rich Nass, Editorial Director, UBM Electronics
ARM has moved down into MCU designs with the introduction of the Cortex-M series and up into new high-speed, high-end applications with the Cortex-A8 and –A9. Both of these directions open up new application spaces for ARM developers while bringing along new challenges. The superscalar 4-core Cortex-A9 MPCore in particular is extremely fast and flexible, but how do you master its complexity in a timely manner? In what applications do the latest ARM chips make the most sense, and what tools, tips and techniques are there to help you implement those designs? Our panelists will address those issues and others and answer them as best they can in the in this informative one-hour webcast.
Moderator: John Donovan, Editor/Publisher, Low-Power Design
Panelists:Ata Khan (Vice President of the Technical Staff, Cypress), Geoff Lees (Vice President and General Manager, Microcontroller Business Unit, NXP), Horacio Mendez (Executive Director, SOI Consortium), Nandan Nayampally (Director, Product Marketing, ARM LTD)