One of the main premises of technology scaling is that the energy per operation must reduce with every new technology node. With CMOS approaching the 22 nm node, that basic assumption may not hold any longer. Reducing the voltage is no longer an option due to leakage, while the capacitance may level off due to fringing and proximity effects. Hence alternative techniques to further increasing computational density at fixed energy costs should be considered. Novel devices with steeper sub-threshold roll-off are one option, but will take at least a decade to make it into mainstream production. A more attractive solution is to consider computational techniques that can operate robustly under much smaller margins and in the presence of a substantial level of noise and random variations. In this presentation, we will explore the opportunities of some of the techniques to do just that such as statistical computing, bio-inspired computing and digitally-assisted analog processing.

Address by: Jan M. Rabaey, Donald O. Pederson Distinguished Professor, University of California at Berkeley

Jan Rabaey received his Ph.D degree in applied sciences from the Katholieke Universiteit Leuven, Belgium. After being connected to UC Berkeley as a Visiting Research Engineer, he was a research manager at IMEC, Belgium. In 1987, he joined the faculty of the Electrical Engineering and Computer Science department of the University of California, Berkeley, where he now holds the Donald O. Pederson Distinguished Professorship. From 1999 until 2002, he served as the Associate Chair of the EECS Dept of UC Berkeley. He is currently the scientific co-director of the Berkeley Wireless Research Center (BWRC), as well as the director of the FCRP Multiscale Systems Research Center (MuSyC).

In one episode of Star Trek Spock's brain enters the ship's computer and takes over control of the Enterprise. That's essentially what power management ICs (PMICs) attempt to do—control a complex IC, to which they're commonly matched, or an entire PCB. On a system level distributed power makes more sense, but coordinating a board or box full of PMICs is a non-trivial task. How do you develop an overall power-supply sourcing and distribution topology which meets many, sometimes conflicting goals? This session will examine the latest strategies and tactics for retaining control of the ship.

Moderator: Colin Holland, European Editor-in-Chief for Embedded Systems

Session Panelists:

• Rick F. Zarr, Technologist, National Semiconductor Corp.
• Steve Rivet, Director, Power Products, Intersil
• Siamak Bastami, Product Line Director, Portable Power, Analog Power Group, Integrated Device Technology
• Ken Marasco, System Applications Manager, Analog Devices

Digital engineers have long had a hard time understanding what their analog colleagues were doing-and neither wants to get anywhere near RF. But with most new designs being mixed-signal and increasingly wireless, that's a luxury designers can no longer afford. This session will explore the issues involved in the integration of analog, logic, and power functions on a single chip, as well as embedded memory.

Moderator: John Donovan, Editor/Publisher, Low Power Design

Session panelists:

• Dr. Qi Wang, Senior Architect and Head of Solutions Marketing Cadence Design Systems
• Barry Pangrle, Mentor Graphics Solutions Architect - Low Power Design
• Jim Davis, PSoC Product Marketing Manager, Cypress Semiconductor
• Geoffrey Ying, Director of Product Marketing, AMS Group, Synopsys

The concern over how to better manage energy consumption across an increasing number of electronic device applications has never been greater. Thanks to advances in semiconductor analog and mixed-signal technologies, we are witnessing power management solutions that would not have been imagined just a few years ago. Not surprisingly, many of these solutions are being driven by the need to improve our energy stewardship as well as the desire to extend battery life for a rapidly expanding range of mobile electronic products. These forces create the perfect storm to take power management solutions to new levels of efficiency and sophistication. However, leveraging the latest advances in semiconductor processing technologies and deploying creative design techniques will be essential. This session will discuss how designers can navigate this perfect storm to innovate power management solutions that meet the needs of emerging consumer and industrial market segments.

Moderator: Stephan Ohr, Senior Analyst, Analog and Power Semiconductors, The Gartner Group

Presenters include:

• Lou Hutter, Senior Vice President, General Manager, Analog Foundry, Dongbu HiTek "Technology Considerations for Emerging Power Management Markets"
• John Pigott, Freescale Fellow and Analog IC Guru and Designer, Freescale Semiconductor "Semiconductor Challenges in Battery Management for Electric Vehicles"
• Ralf Muenster, Director Strategy and Business Development, National Semiconductor "Active Power Management for Solar Systems and Electric Vehicles"
• Wayne Chen, VP Technology and Operations, Triune Systems "Ultra Low-Power Analog: nanoSmart"

As we approach the post-Moore era, hardware designers may be running short of power-saving tricks. Is energy-efficient software-or power management of hardware by software-the way forward, or does that require hardware, software and RF engineers finally being able work together at the system level?

Moderator: Colin Holland, European Editor-in-Chief for Embedded Systems

Panel Discussion: 4:00pmEST - 5:00pmEST

Energy harvesting takes many forms, including solar panels, thermistors, MEMS-based micro generators and nano-generators; storage devices for such tiny charges include thin-film batteries and capacitors. Once an obscure area of only academic interest, energy harvesting is making possible ultra-low-power networks that monitor vibration in aircraft wings, worn motor bearings at power stations and cracks in bridges. As more of an emphasis is placed on generating power while reducing costs, energy harvesting applications are moving to the forefront of engineering design.

Moderator:John Donovan, Editor/Publisher, Low Power Design

Session panelists include:

• Brant Ivey, Applications Engineer, Advanced Microcontroller Architecture Division, Microchip Technology Inc.
• Mark Buccini, Director of Strategic Marketing, Ultra Low-Power Systems, Texas Instruments
• Steve Grady, Vice President of Global Marketing, Cymbet Corp.
• Sam Nork, Director, Boston Design Center, Linear Technology

If batteries aren't going to get much better and the benefits of chip scaling are running out, how do we keep giving those pesky consumer all the features they demand in low-power, portable devices? Can cell phones-not to mention ultra-low power wireless networks-be powered by solar cells, vibration sensors, thermistors, RF harvesting or other energy scavenging schemes?

Moderator: John Donovan, Editor/Publisher, Low Power Design