SAN FRANCISCO. – Samsung will give a first look at its 10nm process technology at the International Solid-State Circuits Conference here in February. ISSCC also will show significant advances in fingerprint recognition, vision processors and 3-D chip stacks as well as denser memories and a novel Mediatek mobile SoC packing ten cores in three clusters.
The event draws about 3,000 chip designers from around the world ranging from students to veteran engineering managers. They come to network with their tribe and compete to deliver papers that put a spotlight on budding talent and industry milestones.
Samsung will deliver several papers including ones detailing advances in DRAM and flash memory chips. But it’s most significant paper will describe a 128Mbit embedded SRAM made in a 10nm FinFET technology.
ISSCC organizers said the device has “the smallest [SRAM] bitcells to date,” measuring 0.040μm for a high density (HD) and 0.049μm for a high current (HC) version. The designs sport “integrated assist circuitry that improves Vmin for the HD and HC bitcells by 130mV and 80mV, respectively,” according to the ISSCC program released Monday.
“Compared to Samsung’s 14nm SRAM at 0.064μm2, the 10nm cell is a 0.63X shrink, certainly less than ideal,” said David Kanter a microprocessor analyst for The Linley Group and Real World Technologies.
“Compared to Intel’s 14nm SRAM cell at 0.049 μm2, Samsung’s cell is about a 0.82X shrink, a consequence of the fact that Samsung didn’t shrink their metal rules between 20nm and 14nm,” said Kanter. “I’d expect Intel’s 10nm SRAMs to be much smaller, but they aren’t sharing that information yet,” he added.
TSMC, one of Samsung’s closest rivals in chip making, announced its 10nm process announced earlier this year. The Taiwan foundry is said to be gearing up the process to make the SoC inside Apple’s next-generation iPhone. Samsung and TSMC split Apple’s current iPhone SoC business, according to reports.
The world’s largest chip maker, Intel Corp., has delayed plans for making 10nm chips, citing the increasing costs and complexity given delays in next-generation lithography needed to draw the finest lines. Samsung and TSMC don’t have that option if that want to win Apple’s business which is probably the highest-volume chip deal in the industry, albeit likely at strained profit margins given10nm chips which will require triple patterning for some key layers.
The Samsung SRAM is the only 10nm part described at ISSCC. The event includes many papers detailing chips made in TSMC’s 16nm FinFET process. A scan of the program found none made in Samsung’s rival 14nm process.
Intel may shed a little light on the increasing difficulty and costs making next generation chips in a keynote at the event. William M. Holt, general manager of Intel’s manufacturing group, will give a talk entitled, “Moore’s Law: A Path Forward.”
A description of the talk admits “there are growing concerns and doubts over the vitality of Moore’s Law going forward, given the scaling challenges we face.” Besides describing Intel’s current 14nm process, the “talk will also discuss some leading technology options on the horizon beyond CMOS and their potential design benefits in advancing Moore’s Law well into the future. Novel 3D heterogeneous integration schemes and new memory technologies will be discussed for their potential in optimizing the memory hierarchy and addressing bandwidth challenges in processor performance and power,” according to the ISSCC materials.
Next page: 3-D stacks rise above Moore’s Law challenges
That 10nm of Samsung looks very close to Intel's 14nm, in terms of SRAM size. You can't win Moore's Law by renaming your process nodes to smaller numbers.