BRUSSELS — Looking down the semiconductor road map, researchers at the Imec research institute see small, medium and large challenges on the horizon. In presentations and interviews at their annual event here, they and some of their partners shared a bit of what’s ahead.
Reducing costs per transistor at the next-generation, the 10nm node, will be tricky. Even more challenging will be getting extreme ultraviolet lithography ready to enable a full 7nm node.
Further out, scaling to and beyond the 5nm node may require a whole new kind of chip technology. Increasingly experts speculate the answer will emerge as some sort of stacking that is not yet on the whiteboard.
The mid-term challenges are currently the most pressing. The 7nm process will be an expensive half node if the long delayed extreme ultraviolet lithography systems are not ready for early production in 2017.
Researchers here are upbeat EUV will arrive in time, but there are plenty of challenges ahead:
- The light source needs an upgrade to at least 180W, up from today’s best demo of 110W at ASML.
- The systems need to be available at least 80% of the time, up from an average of about 50-60% today.
- Systems need to increase throughput from 70-80 wafers per hour to something closer to the 200 w/h of today’s immersion steppers.
- Resists need to be more sensitive to work at lower doses with less rough edges.
- New protective wafer covers, called pellicles, may need to be designed to replace the initial pellicle ASML is now supplying its customers for use at the relatively low 80-110W power levels.
- Improvements are needed in finding and fixing defects.
“We are confident EUV will enter manufacturing most likely starting at the 7nm node,” Luc Van den Hove, chief executive of Imec said at a press conference here.
He should know. The institute has spent as much as $1.3 billion on a state of the art research fab that has been working with EUV systems for years. It currently houses one of about eight of the latest systems installed worldwide.
Nearly all the top chip makers partner with Imec on pre-competitive research on next-generation nodes. This year Toshiba and Sandisk, two of the few holdouts, joined the program.
In a talk here, the head of ASML, the Dutch company developing EUV, gave a few new proof points of progress. One customer achieved for one week an 82% up time for one system, the NXE 3300B. ASML has a program targeting by the end of the year up time of 86% for the volatile light source.
The system is as critical as it is complex and troubled. Trillions of dollars are at stake in continuing the process of scaling to ever smaller chips, said Peter Wennik, chief executive of ASML in a talk here. “It’s a machine with a lot of industrial engineering problems — a whole slew of problems we will resolve one by one,” he said.
Indeed every time ASML ratchets up the power on the light source which is critical to the throughput of the machine, some problem emerges in another module that has to be upgraded or redesigned to keep the machine running. “It’s a process of continuous engineering,” said Kurt Ronse, who heads the lithography program at Imec.
Next page: Without EUV, 7nm is a half node
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Will EUV arrive in time to fend off quintuple patterning at 7nm?