Richardson, Texas– Oct. 14, 1997–Cyrix Corp. revealed the internal architecture of its next processor core, code named Cayenne, at Microprocessor Forum '97.
Cayenne will feature a fully pipelined, dual-issue floating pointunit and 15 new MMX floating point instructions to enable high-performance 3D graphics, DVD, and 3-D audio.
A key component of the Cayenne core is the ability to execute four floating point operations per cycle using dual MMX units. This will deliver over 1 GFLOP peak performance. In addition, the dual floating point reciprocal and reciprocal-square-root instructions will execute five times faster on Cayenne than on the Pentium II processor. These instructions are used extensively in lighting calculations for 3-D image processing.
The net result is that Cayenne will deliver in excess of 10 million meshed triangles per second to an external 3-D rendering engine–more than five times faster than the Pentium II processor. Lastly, Cayenne will deliver single-cycle throughput on standard x86 floating point instructions.
The Cayenne core will feature a dual-issue floating point and MMX unit, 64-kbyte L1 cache, and an enhanced sixth-generation integer unit. Processors based on the core will initially be manufactured using a 0.25-(m, 5-layer metal process. This includes a C4 process for flip chip assembly. As a result, the core die size is expected to be about 65 mm-squared. Processors based on this core are expected to be in production in the second half of 1998 at speed ratings ranging from PR300 to PR400.
Cyrix
http://www.cyrix.com
Leave a Reply
You must Register or Login to post a comment.