SAN JOSE, Calif. — The Cyrix division of National Semiconductor Corp. described its Jalapeno core as a 600-MHz “memory centric” design that will be used in Cyrix's M3 family of processors, which will begin sampling late in 1999.
The design will include a Rambus ASIC cell as an on-chip memory controller that will support 3.2-Gbytes of bandwidth between the processor and a Rambus in-line memory module (RIMM).
With its CPU rather than a separate memory controller handling main memory accesses, Cyrix may be the first vendor to market an X86 core with an on-chip Rambus access controller. Michael Slater, editorial director of Microprocessor Report , and forum's sponsor, said he believes Intel and other competitors will also move to an on-chip memory controller, and to an on-chip L2 cache. Slater made a flat prediction that nearly all microprocessors will put L2 cache directly on-chip by 2000. That's “bad news for the SRAM vendors,” he said.
Jalapeno includes 256 kbytes of on-chip L2 memory, and 16 kbytes of L1 cache.
Greg Grohoski, architect of the Jalapeno, said the cache structure of the device has the intelligence to detect misses, so “our 256-kbyte cache acts like a 512-kbyte cache from other companies.
“One-fourth to one-half of all L2 misses are predictable, so we worked to develop an 8-way associative cache that has pre-fetch intelligence,” he said. “In this design we did everything we could to reduce memory latency.”
The Jalapeno core includes an integrated 3-D graphics controller. On-chip memory and fast access to the RIMM results in a unified memory architecture, Grohoski said. The core's graphics front-end can process 3 million polygons a second, he said.
The core is designed to run at 600 MHz with an 11-stage pipeline. It is a dual-issue design with out-of-order execution and register-renaming capabilities.
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