SANTA CLARA, CALIF. — The PCI Special Interest Group has determined it can squeeze out of copper links at least one more high speed version of PCI Express before a likely transition to optical interconnects. PCIe Gen 4 is expected to deliver at least 16 GTransfers/second when it debuts in products in about four years.
“The initial report we got yesterday is a PCI Express 4.0 is feasible–we have to work out the details, but it is feasible,” said Al Yanes, president of the PCI SIG, speaking in a press briefing at the group's annual developers conference .
A exploratory group including members from AMD, Hewlett-Packard, IBM and Intel are conducting simulations using chip, channel, packet and socket data. They have determined throughput of at least 16 GT/s is possible and are expected to deliver a final report before the end of the year.
“We think we can eke out one more turn of the crank out of copper, so we are not looking at optics yet,” said Ramin Neshanti, chairman of the PCI SIG's serial communications working chair.
It took the PCI SIG about four years to hammer out its 8 GT/s PCIe Gen 3 spec which required new signal encoding and equalization schemes. The Gen 4 spec should take a similar period, but this time the focus will be less on silicon and more on the board-level channels through which signals pass, Neshanti said.
Specifically, Gen 4 will probably be limited to distances of about eight to 12 inches compared to 20 inches for Gen 3. Engineers wanting longer reaches will need to use repeaters, a potential growth area for PCIe silicon.
The Gen 4 boards may need to use new materials, via designs and backwards-compatible connectors designed for improved signal integrity to reduce impedance discontinuities. “We think we have achieved about as much as we can scaling silicon,” said Neshanti who also serves as an I/O standards manager at Intel.
That's a big shift for the PCIe community which has not previously required major changes of board makers. Typically the PCI SIG has thrown its hardest problems to chip makers such as AMD, Intel, NEC and others to ease problems for its less technically sophisticated supply chain among high volume PC board and system makers.
Nevertheless, some significant silicon shifts are ahead. Transceivers for Gen 3 were the first to use techniques to massage signals, adopting single-tap decision feedback equalization (DFE).
Gen 4 transceivers will need to use multi-tap DFE. How many taps they will need is not yet clear.
“There also will be heavy investments needed from test equipment vendors to do some very creative probing solutions either on chip or somehow as an add-in,” said Neshanti. Agilent, LeCroy and Tektronix are among the testers involved in the work, “but we don’t know which will step up first,” he said.
Work has so far focused on electric and analog aspects of the physical-layer design for PCIe Gen 4. Over time, exploration will start on logical-layer and protocol improvements in areas such as latency reduction, forward error correction, deeper pipelining and error reporting and control.
At the end of the day, costs are expected to increase with the new generation, especially for applications that need to maintain today's longer distances. But the group aims to keep additional costs to a minimum.
“PCI Express lives and breathes because of its ubiquity and that comes based on its low cost,” said Neshanti.
The need for speed is clear. Graphics and network switches are among the most bandwidth-hungry applications driving Gen 4. Designers of dual-port 40 Gbit/s Ethernet and single-port 100G Ethernet boards want Gen 4 to avoid the costs of supporting the pins they otherwise need for 16 lanes of PCIe Gen 3.
“Adapter vendors like to be around [eight-lane] implementations for cost reasons,” said Yanes.
Meanwhile, engineers are making progress getting 8 GT/s PCIe 3.0 products out the door. At least 14 companies with building block cores, software or testers have announced Gen 3 support.
To date about 23 adapter cards and 19 systems from top PC makers have participated in the PCI SIG's Gen 3 plugfests. “Their products are in prototype phase and haven’t achieved full debug interoperability, so they are not ready to announce them,” said Yanes.
The PCI SIG hopes to publish by early next year a list of products that have passed interop tests. The group plans at least three more plugfests in Silicon Valley and Taiwan this year.
“PCI Express Gen 3 is more sophisticated in its electrical design [than past PCI SIG standards], so we are giving members more feedback on how they are doing” with their first products, said Neshanti.
Anticipating the future, PLX Technology demoed at the PCI dev con eight lanes of PCI Express 3.0 linking systems over optical cables at 64 Gbits/s.
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