Facebook Likes Intel's 3D XPoint
Slideshow 3/10/2016 7 comments
Facebook endorsed Intel’s 3D XPoint memories and got Google to join its Open Compute Project at its annual event that included new processors from Intel and networking code from Microsoft.
Red Hat Drives FPGAs, ARM Servers
News & Analysis 2/12/2016 3 comments
Red Hat’s chief ARM architect is rallying FPGA makers to set a software standard for accelerators in between trying to get ARM servers ready for the market.
Google's Deep Learning Comes to Movidius
News & Analysis 1/27/2016 Post a comment
Google will buy Movidius vision processing chips and license the entire Movidius software development environment. Google's goal is to expand its machine intelligence technology beyond the data center, by bringing it to mobile devices.
FPGA Interfaces Speeding Up
Blog 11/16/2015 16 comments
IBM and Xilinx have joined the race to bring FPGA accelerators to data centers. The problem they and their competitors have yet to solve is delivering an easy-to-use standard interface for them, according to a Red Hat executive.
Dell Preps Semi-Custom Servers
News & Analysis 10/22/2015 Post a comment
Dell unveiled new servers for the data center market and enterprise at its annual DellWorld conference, targeting custom and semi-custom network infrastructure and storage for tier two cloud providers and others.
Xilinx Revenues Driven By Data
News & Analysis 10/14/2015 Post a comment
Xilinx's second quarter fiscal 2016 sales were down 4% from the prior quarter and down 13% year-over-year, but Xilinx's CEO put emphasis on its data-center future.
Intel Rides Servers, Flash in Q3
News & Analysis 10/13/2015 2 comments
Intel today reported third quarter revenue of $14.5 billion, a 10% increase from the second quarter of 2015, and flat year-over-year. Growth in its data center, non-volatile memory, and Internet of Things businesses offset lower client revenue.
Put FPGAs In Your SoCs
News & Analysis 10/2/2015 5 comments
Flex Logix has a new type of FPGA that nearly doubles the number of usable gates per chip. The FPGAs eliminate more than 20% of the room needed for interconnect and switches, and now have nearly 50% more room for gates.
8+ Horizons at Hot Chips
Slideshow 9/1/2015 Post a comment
The chip horizon is bright and diverse said speakers at Hot Chips presenting on 5G cellular, neural networks, molecular diagnostics, chip stacks and FPGAs.
Should Altera Worry About Intel's M&A Record?
News & Analysis 8/17/2015 13 comments
Altera’s fate after its pending acquisition by Intel is anybody’s guess. But the big worry is if Intel squashes Altera -- pushing newly acquired talent, products and technologies into oblivion as though they had never existed.
The History of Jitter
Blog 7/27/2015 2 comments
Jitter, that pesky little timing error in high-speed serial links, has a history that longer than billions of unit intervals.
Chip Stacks at 30,000 Feet
Blog 6/22/2015 2 comments
A chance encounter on a plane with Nvidia’s Jen-Hsun Huang shed just a little light on the road to chip stacks as Moore’s Law slows.
Smart Glasses Strap On AR
News & Analysis 6/10/2015 Post a comment
Emerging technologies like AR comes with a series of challenges and opportunities, executives from smart glasses and AR device companies said during a session. Still, as additional use cases develop the possibilities are endless.
Synthesis Engine Boasts 10X RTL Design Productivity
News & Analysis 6/8/2015 Post a comment
The Cadence Genus Synthesis Solution is the EDA company's next-generation register-transfer level (RTL) synthesis and physical synthesis engine, incorporating a multi-level massively parallel architecture that is claimed to deliver up to 5X faster synthesis turnaround times while scaling linearly beyond 10M instances.
Intel, Altera: Math in Question
News & Analysis 6/1/2015 34 comments
Analysts said Intel and FPGA vendor Altera will see benefits from their $16.7 billion merger, but question the math and assumptions behind the deal.
SoC RTL Signoff: Divide & Conquer with Abstract Models
Blog 6/1/2015 Post a comment
One of the fastest, easiest, and most effective methods to detect and remove bugs early in the design phase, is to run lint checks on the RTL. Besides coding guidelines, these tools catch issues related to simulation, synthesis, and place & route. A robust lint methodology reduces long and costly iterations between RTL design and downstream verification and implementation.
FPGAs Ride HP’s Moonshot
News & Analysis 5/28/2015 18 comments
SRC Computers announced a new FPGA server card that Hewlett-Packard will sell as an option for its processor-agnostic Moonshot servers.
Intel, Altera, Moore...and Drinks
Blog 5/22/2015 7 comments
The on-again, off-again Intel/Altera acquisition was the talk of a cocktail hour sponsored by Imagination Tech where tech execs talked of Moore’s Law and VR.
Visualizing Better Protocol Debug
Blog 5/6/2015 Post a comment
The many wheels of technology, as much as we’d like them to, don’t move ahead in lockstep fashion. Sometimes the demands of one technology outrun the benefits of an enabling technology.
Moore’s on at 28nm
Blog 5/5/2015 19 comments
Moore’s Law is not ending soon, yet it is not going to be the simple brute-force x0.7 dimensional scaling that dominated the industry for the last 5 decades.
Lattice Deal: Harbinger of FPGA & ASSP Union
News & Analysis 5/1/2015 2 comments
Lattice CEO, after its acquisition of Silicon Image in March, believes the marriage of FPGA company to an ASSP firm is a match made in heaven. He said, “That’s why Intel wants Altera. It’s obvious.” But is it?
Athena Security IPs Designed to Mend Holes in SoCs
News & Analysis 4/21/2015 6 comments
We see rapidly growing needs for protecting connected systems by using security chips with crypto keys inside. But how do we know if security chips themselves (designed into such connected systems) aren’t leaking key information?
Industrial IoT Drives Microsemi-Vitesse Merger
News & Analysis 3/18/2015 Post a comment
Microsemi Corp. will acquire Vitesse Semiconductor Corp. for $389 million to focus on “communications semiconductors.” On horizon is the MIPS vs. ARM conflict as the two companies use two diverging processor cores of their product lines.
Marvell Shakes Up SoCs, DRAMs
News & Analysis 2/23/2015 10 comments
Marvell CEO Sehat Sutardja announced a new SoC interconnect and virtual-memory initiatives aimed to make next-generation chips and systems cheaper.
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