REGISTER | LOGIN
Breaking News
Content tagged with Design Tools (EDA)
posted in October 2011
<<   <   Page 3 / 3
Opinion: Is DV the ladder to nowhere?
Engineering Pop Culture!  
10/4/2011   9 comments
We all have opinions and they are a great way to get conversations started. Here is one from my friend Lewis Sternberg who believe that being in verification limits your future...
Swatch chip arm qualifies Bluetooth LE chip
Product News  
10/4/2011   4 comments
EM Microelectronic-Marin SA, the semiconductor division of the Swatch Group, has announced that its EM9301 Bluetooth low energy radio chip has received Bluetooth V4.0 qualification.
Machinarium Ė One of the most amazing computer games Iíve ever seen!
The Engineering Life - Around the Web  
10/3/2011   5 comments
I keep telling myself that I donít play computer games, but I just realized that Iím currently devoting hours of my time to an amazing creation called MachinariumÖ
Oooohhhh, Shiny!!! The BMW i8 concept car
Engineering Pop Culture!  
10/3/2011   2 comments
Iím not usually much interested in cars, but in the case of the BMW i8 I will make an exceptionÖ
Springsoft becomes more open
Blog  
10/3/2011   Post a comment
When things become open, they tend to get used more and that is the primary intent for Springsoft as they open up access to the FSDB and KDB dataÖ
How It Was: PCB Layout from Rubylith to Dot and Tape to CAD
Programmable Logic DesignLine Blog  
10/3/2011   9 comments
Dot and Tape refers to the product used to lay the patterns of tracks and IC/transistor pads on to mylar sheets; before Dot and Tape there was Rubylith...
Debunking the myth of the $100M ASIC
Blog  
10/3/2011   17 comments
A false belief that leading-edge chips cost up to $100 million to develop has severely decimated levels of venture capital investment in semiconductors, diminishing innovation.
Startup offers embedded memory IP
News & Analysis  
10/3/2011   1 comment
Memoir Systems Inc. is a 2009 startup company that has begun offering embedded memory intellectual property aimed at SoCs being designed for the networking and multicore processor markets.
Travel Nightmares: Lou Covey assumes a new identity
Blog  
10/3/2011   1 comment
Traveling can always mean problems and in our continuing series about travel nightmares, Lou Covey recounts one of his problematic journeys...
Reducing Turnaround Time with Hierarchical Timing Analysis
Design How-To  
10/3/2011   1 comment
STA is a key task during chip design that directly impacts design cycle time. Hierarchical techniques are used to break down design complexity into manageable units...
<<   <   Page 3 / 3


Like Us on Facebook
EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Martin Rowe

Test Tool Finds Ethernet Wiring Errors
Martin Rowe
Post a comment
When my house was renovated several years ago, I had the electrician install network outlets in numerous places, then run the LAN cables to a wiring closet. But he didn't document the ends ...

Martin Rowe

Local Electronics Store Supplies Engineers and Hobbyists
Martin Rowe
5 comments
Rochester, N.Y. — Tucked away in this western New York city known for its optics is Goldcrest Electronics, a local store that's supplied businesses and individuals with electronic ...

Martin Rowe

How to Transform a Technology University (Book Review)
Martin Rowe
1 Comment
The Presiding Genius of the Place by Alison Chisolm. WPI, Worcester, Mass., 234 pp., 2016. Engineers love to discuss, and often criticize, engineering education. They often claim ...

Max Maxfield

Aloha from EEWeb
Max Maxfield
Post a comment
Just a few minutes ago as I pen these words, I posted this blog about this month's Cartoon Punchline Competition over on EEWeb.com.