Verification Platform for Complex Designs
Design How-To 12/31/2007 Post a comment
In this article the challenges faced in verifying today's complex designs are discussed. Along with, the corresponding advancements required in verification products and techniques to overcome these issues have been suggested.
Get research out of development
Blog 12/26/2007 Post a comment
An engineer is a professional that uses available tools to develop the best possible solution to a problem. A scientist is a professional that explores new possibilities within a given field with the goal of creating new engineering tools.
Understanding Clock Domain Crossing Issues
Design How-To 12/24/2007 7 comments
In today's complex system on chip (SoC) designs, multiple clocks have become the norm. Thus, clock domain crossings (CDCs) are an integral part of any SoC. The main problems which can occur in a clock domain crossing are metastability, data loss and data incoherency. In this paper, we discuss all these issues for different types of synchronous and asynchronous clock domain crossings.
Free DSP cores!
Signal Processing DesignLine Blog 12/17/2007 Post a comment
Structured ASIC company eASIC now offers Tensilica cores free of charge. If you have a medium-volume app, you should check this out.
Achieving Yield in the Nanometer Age
Design How-To 12/17/2007 Post a comment
Designers and manufacturers are two sides of the same team, sharing a common goal " yield. To win out, they need to align their strategies, their skills and their knowledge, and work together to overcome the challenges. That's the way the game is played in the nanometer era.
ARC configures a design flow for system-on-chip
Design How-To 12/12/2007 Post a comment
Configurable cores and subsystems developer ARC International (St. Albans, England) has developed and is refining a systems development platform that it says will change the way mobile multimedia systems are being designed.
Tensilica enhances Xtensa cores and tools
Product News 12/11/2007 Post a comment
Tensilica has shrunken the minimum core size of its Xtensa 7 and Xtensa LX2 configurable processor families. It has also enhanced the Xtensa Xplorer design environment to make customization easier and faster.
MATLAB to C showdown
Signal Processing DesignLine Blog 12/11/2007 Post a comment
Catalytic MCS and Embedded MATLAB both generate C from MATLAB, but there are big differences between the products. Here's the scoop.
ATopTech Releases Aprisa
Product News 12/10/2007 Post a comment
Aprisa is a netlist-to-GDSII physical design solution that includes floorplanning, placement, clock tree synthesis (CTS), global routing, and detailed routing.
Virtually every ASIC ends up an FPGA
Design How-To 12/7/2007 Post a comment
Because more than 90 percent of all ASICs today are either partially or completely prototyped in FPGAs before tape-out, the question is no longer whether to implement an IC design as an ASIC, or as an FPGA. To meet the demands of today's markets, most design teams must do both.
Using DFM Routing to Impact Design Performance and Yield
Design How-To 12/4/2007 Post a comment
As design teams continue to drive forward with the use of advanced process technologies there has been much discussion about the use of design-for-manufacturing (DFM) techniques and questions about the real usefulness and effectiveness of DFM. This paper describes an experiment conducted to establish the quantitative performance and yield impact of proactively using DFM techniques during the routing of a design.
MATLAB-to-C tool get major upgrade
Product News 12/3/2007 Post a comment
Catalytic's MATLAB-to-C tool can now generate C code for over 300 MATLAB functions, including functions from the signal processing, communications, imaging, and math toolboxes.
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