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Content tagged with Design Tools (EDA)
posted in July 2011
Cadence lifts sales target after strong Q2
News & Analysis  
7/29/2011   1 comment
Cadence Design Systems adjusted its sales target for 2011 after reporting revenue for the second quarter that beat consensus analysts' expectations.
The Periodic Table of Programmable Logic – Rev #1
Programmable Logic DesignLine Blog  
7/28/2011   43 comments
Wow! Just yesterday as I pen these words I posted my blog suggesting that we might create a Periodic Table of Programmable Logic and I’ve been overwhelmed by the response…
SofCheck preps ParaSail parallel language
7/28/2011   10 comments
SofCheck Inc., best known as a vendor of software analysis and verification technology and Ada Compilers, is working on a parallel programming language called ParaSail that has been presented at two learned conferences recently. Finding the right part just got easier
7/28/2011   24 comments
With the launch of, EDN and UBM Electronics provide engineers access to over 185 million parts, with features such as comparison, parametric search, search save, and alerts.
Composite supersets tame wiring harness engineering complexity
Design How-To  
7/28/2011   Post a comment
With many electrical options and physical variants in today's cars, potential configurations for a single platform may number in the millions. Thus the electrical distribution system harness is at the heart of the automotive complexity challenge.
Periodic Table of Programmable Logic
Programmable Logic DesignLine Blog  
7/27/2011   12 comments
Now here’s something you don’t see every day…
MIT Professor uses ESL tools and FPGAs to teach system architecture
Design How-To  
7/27/2011   3 comments
Using modern design tools and development platforms – it is possible to quickly express and evaluate alternative architectures so as to come up with optimal implementations.
Gray Code Fundamentals – Part 5
Design How-To  
7/26/2011   1 comment
In this, the fifth and final installment of our mini-series, we ponder the concept of "n-ary" (non-Boolean) Gray codes.
Co-design – Myth or Reality?
7/26/2011   13 comments
We are now on the right track to co-design, rather than the track that the early research took.
Book Review: 100 Power Tips For FPGA Designers by Evgeni Stavinov
Engineer’s Bookshelf  
7/25/2011   5 comments
In many ways this is an unusual book – one that will provide something of interest to almost every reader…
A cornucopia of iPad apps (Part 1)
Engineering Pop Culture!  
7/25/2011   3 comments
Is it really just a little more than a month ago that I took the plunge and purchased an iPad? I find that hard to believe, because I can’t remember life without it…
Optimal Skew
Design How-To  
7/25/2011   2 comments
Minimizing clock skew across the network may result in high power and timing difficulties. This paper suggests careful selection of clock skews.
SparkFun electronics training for kids
7/25/2011   3 comments
The folks at SparkFun have a bunch of interesting training courses coming up for kids who live in or near Boulder, Colorado.
Flat versus hierarchical PCB design – which is best?
7/22/2011   5 comments
I would be very interested to hear what you like with regard to flat and/or hierarchical PCB design techniques.
Do NOT read this blog!
Programmable Logic DesignLine Blog  
7/22/2011   76 comments
It seems that henceforth I may have to include disclaimers with any of my blogs that are on non-programmable-logic-related topics saying…
GPS Car locator app for droid smartphones
Programmable Logic DesignLine Blog  
7/22/2011   4 comments
Car Locator, which is available from the Android Market and the V CAST App Store, is a very clever application.
Xilinx new rad-hard Virtex-5QV FPGAs – what a good idea!
7/21/2011   Post a comment
I am really excited by today’s announcement by Xilinx as to their new space-grade rad-hard Virtex-5QV FPGAs. Why? Let me explain...
Xilinx space-grade SRAM-based Virtex-5QV FPGA in production with Mega-Rad capability
Product News  
7/21/2011   1 comment
Designers now have the ability to replace ASICs and one-time-programmable (OTP) solutions with space-grade, high-density, rad-hard reconfigurable FPGAs.
Taiwan nurtures the next ARM
News & Analysis  
7/20/2011   13 comments
Meet Andes, Taiwan's answer to ARM.
Introducing a new high-level synthesis tool called HercuLeS
7/20/2011   4 comments
One of the great things regarding my being the editor of Programmable Logic Designline is that I get to hear about all sorts of cool things, such as…
Embedded software firm gets angel funding
News & Analysis  
7/19/2011   2 comments
The Indian Angel Network has invested $1 million in embedded software tool developer Vayavya Labs to help the firm expand its tool suite for electronic systems level design and bolster its sales and marketing efforts.
Free Webinar: Prototyping multi-million-gate ASIC designs
7/19/2011   1 comment
Learn how new FPGA-based prototyping systems from Synopsys enable early HW/SW validation, debug, and development for much larger SoC projects than ever before.
Xilinx Xcell Journal wins two “Awards of Excellence”
7/19/2011   1 comment
I must admit that I’ve long been a fan of the Xcell Journal quarterly magazine from Xilinx. This is a high-quality publication that always features a wide variety of interesting articles.
Virtualizer – Next-gen virtual prototyping solution from Synopsys
News & Analysis  
7/19/2011   Post a comment
Virtualizer is claimed to accelerate software development schedules by up to nine months with lower engineering effort
Radar basics – Part 5: synthetic aperture radar
Design How-To  
7/18/2011   10 comments
Synthetic Aperture Radar, or “SAR”, is normally used to map ground features and terrain.
Am I a racist? Are you?
Programmable Logic DesignLine Blog  
7/18/2011   27 comments
I just took an online test described in Malcolm Gladwell’s book “Blink: The Power of Thinking Without Thinking.” The result has certainly given me something to ponder…
I want to build a “Hassler” – does anyone have the circuit?
Programmable Logic DesignLine Blog  
7/14/2011   16 comments
This is an audio circuit that generates interference when someone speaks loudly – it provides a way to “train” your colleagues to speak in a softer tone.
Free webinar – Creating high-reliability, high-availability designs using FPGAs
7/13/2011   2 comments
This one should be a lot of fun, not the least that yours truly (yes, me, myself, I) will be acting as the host…
Embrace your inner geek!
Programmable Logic DesignLine Blog  
7/13/2011   3 comments
Did you know that July 13 is “Embrace Your Geekiness Day"? (This is not to be confused with Geek Pride Day, which is celebrated on 25 May)
MathWorks Simulink Design Verifier 2.0 speeds debugging
Product News  
7/13/2011   Post a comment
MathWorks announced that Simulink Design Verifier now includes Polyspace analysis technology for automated error detection in Simulink models.
Product How-To: Controlling Power in Cypress Programmable SoC (PSoC) devices
Design How-To  
7/12/2011   2 comments
The focus of this article is on low power concepts that relate to shutting down power to blocks in a Programmable SoC (PSoC) device from Cypress.
Xilinx continues fast rollout of 28 nm 7 Series FPGAs
7/12/2011   Post a comment
I just heard that the folks at Xilinx have started shipping the first member of their Virtex-7 family of 28 nm FPGAs – the VX485T – to advanced customers.
Veridae had a Very Good Day
7/12/2011   3 comments
We look towards the startup companies for significant changes in direction or new ways to approach existing problems…
Cadence acquires power specialist Azuro
News & Analysis  
7/12/2011   7 comments
Cadence followed up an earlier deal to buy EDA vendor Altos with the acquisition of power specialist Azuro.
SiliconBlue launches 40nm mobileFPGA family (code name “Los Angeles”)
Product News  
7/11/2011   1 comment
Custom ultra-low-power mobileFPGA platform provides high-speed sensor management, custom connectivity, and video and imaging solutions.
Synopsys tips 65-nm PDKs for Globalfoundries
News & Analysis  
7/11/2011   Post a comment
EDA and IP vendor Synopsys collaborated with Globalfoundries to develop, validate, support and distribute interoperable process design kits for Globalfoundries' mainstream and advanced process technologies.
Where have all the Mentors gone?
Programmable Logic DesignLine Blog  
7/11/2011   23 comments
I just received an email from a young engineer that made me feel rather sad… maybe we can offer this youngster some sage advice…
Do you remember … the world before USB?
Programmable Logic DesignLine Blog  
7/8/2011   27 comments
Do you remember how painful working with computers used to be with things like PS/2 connectors, RS-232 connectors, Centronics interfaces, SCSI interfaces, and goodness knows what else?
Efficiency of half-bridge vs. inverter DC/DC power topologies (Part 2 of 2)
Design How-To  
7/8/2011   2 comments
Understand how efficiency is partially determined by the supply topology
New Xilinx ISE Design Suite 13.2 boasts all sorts of cool stuff
Product News  
7/6/2011   Post a comment
Steps up designer productivity, brings partial reconfiguration to Kintex-7 and Virtex-7 FPGAs, improves QoR, enhances PlanAhead, and continues delivering on Plug-and-Play IP initiative
Tektronix buys validation tool vendor
News & Analysis  
7/5/2011   3 comments
Test and measurement vendor Tektronix announced the acquisition of ASIC/FPGA prototyping debug software provider Veridae Systems. Terms of the acquisition were not disclosed.
Traveling through time – what trade goods would you take?
7/5/2011   35 comments
Recently I’ve been pondering what to pack if I were given one day to prepare for a one-way trip into the past or the future…
How to accelerate genomic sequence alignment 4X using half an FPGA
Design How-To  
7/5/2011   1 comment
C-based approach shortens time to accelerate processing on FPGA hardware
Ultra-large-scale FPGA-based SoC dev platforms from Logicview
7/5/2011   Post a comment
Recently Brian Bailey said in a blog that FPGA-based prototyping was going to be the hot topic at DAC 2011. He was right, and since then the news keeps on coming…
PCIe 2.0 compliant low-cost FPGAs from Lattice
Product News  
7/5/2011   1 comment
LatticeECP3 PCI Express IP core solution enables low cost, low power single-chip programmable PCIe 2.0 endpoints.
Digital Blocks’ DB9100 BitBLT 2D graphics engine Verilog IP core family accelerates graphics display apps
Product News  
7/5/2011   Post a comment
New core accelerates graphics development for ASIC, ASSP, and FPGA design teams while off-loading the graphics function from the main Processor and enhancing software developer productivity.
Another clever and funny video from Lattice Semiconductor
7/5/2011   4 comments
I have to take my hat off to the guys and gals at Lattice for coming up with these funny videos that manage to make you laugh while still being informative.
Microsemi achieves AS9100 Rev C and ISO 9001 certifications
Product News  
7/5/2011   Post a comment
Microsemi says it is the first FPGA supplier to achieve compliance with key aviation, space, and defense-quality system requirements
Google’s Android@Home – The plot thickens…
7/2/2011   11 comments
I have a very happy smile on my face, because I now have 100% confirmation as to the wireless protocol used in Google’s recent Android@Home demonstrations…

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Martin Rowe

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Max Maxfield

Aloha from EEWeb
Max Maxfield
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Just a few minutes ago as I pen these words, I posted this blog about this month's Cartoon Punchline Competition over on