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posted in August 2002
SoC-based designs challenge traditional design flows
Design How-To  
8/30/2002   Post a comment
When the semiconductor division of Philips undertook the ambitious task of designing a family of microcontrollers that would remove all the impediments to migration from 8- to 32-bit architectures, we knew that our primary objective was to eliminate the cost barriers while at the same time ensuring deterministic, real-time performance and adequate bandwidth in a package small enough to be deployed in a variety of small-footprint embedded control applications.
SoC-based configurable systems replace the microcontroller
Design How-To  
8/30/2002   Post a comment
Many products once designed using 8-bit microcontrollers with external digital and analog circuitry are being re-designed using SoC devices.
Method ensures on-track designs
News & Analysis  
8/19/2002   Post a comment
Achieving functional closure on register-transfer-level designs continues to be one of the greatest challenges for today's ASIC and system-on-chip design teams.
Library promotes common standard for design properties
Design How-To  
8/19/2002   Post a comment
The Open Verification Library (OVL) provides a standard set of assertion modules that not only enhance simulation but also ease the adoption of RTL formal verification tools.
Design closure becomes elusive for the SoC generation
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8/19/2002   Post a comment
Computer scientists use the term "combinatorial explosion" to describe what happens when variables are added to certain difficult-to-execute algorithms.
Design Closure
Design How-To  
8/19/2002   Post a comment
ASIC design flow gives CPU core custom performance
Design How-To  
8/19/2002   Post a comment
The ever-increasing levels of CPU performance demanded by embedded applications and product design cycles that have often been reduced to only a few months, have made it important to produce synthesizable processor cores capable of execution speeds typically only achievable by complex custom solutions.
A silicon virtual prototype is key in achieving design closure
Design How-To  
8/19/2002   12 comments
The silicon virtual prototype (SVP) emerged as one of the strongest themes from this year's Design Automation Conference in New Orleans.
A case for using FPGAs in SDR PHY
Design How-To  
8/9/2002   Post a comment
Software-defined radio (SDR) technology is undergoing a difficult birthing process.
CAUTION: Mandatory Methodology Shift Ahead
Design How-To  
8/8/2002   Post a comment
The spiraling expense and design time associated with chips fabricated in ever-shrinking design technologies is impacting how and when a chip designer hands off a design to the system designer. Tera Systems' Mark Miller discusses the pros and cons of RTL and gate-level handoff and how both require early awareness of the implications of the design's micro architecture along with high-quality RTL code.


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Aloha from EEWeb
Max Maxfield
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Just a few minutes ago as I pen these words, I posted this blog about this month's Cartoon Punchline Competition over on EEWeb.com.