Programmable Logic DesignLine Blog 8/29/2012 11 comments
My knee-jerk reaction was "Oh dear, what have I said or done that has raised my friend's ire?"
EDA/IP Weekly Roundup – August 29th
Blog 8/29/2012 Post a comment
Sonics, Intel, IMS, TSMC, Amkor, Bluetooth, Samsung, ASML, ARM, Synopsys, Altera, Xilinx, Delft, Open-Silicon and Evatronix made the lineup today. See here for their news…
Design How-To 8/27/2012 Post a comment
Layer-aware optimization is a necessity at 28nm and below to better predict system performance and ensure efficient design closure...
What were they thinking: sock wedgie
Blog 8/24/2012 6 comments
On Fridays, I love to find some humor for the week, and patents are often a source of inspiration. Here is one I found for a problem I didn’t know existed – a sock wedgie…
ASSET releases IJTAG tutorial
Blog 8/23/2012 4 comments
IJTAG could bring some standardization to the usage of on-chip instrumentation, a move that will help make this a much easier task in SoC design…
Synopsys raises profit target again after strong quarter
News & Analysis 8/22/2012 Post a comment
EDA and IP vendor Synopsys raised its profitability target for its current fiscal year for a second consecutive quarter after reporting sales in line with expectations and profitability that exceeded analysts' estimates for the quarter ended last month.
Cheesy Sci-Fi TV Series of the 60s and 70s
Programmable Logic DesignLine Blog 8/22/2012 92 comments
Here are some of the cheesy Sci-Fi TV Series I used to watch in the 60s and 70s. Did you see these? If so, which did you like the best (and which did you hate the most)?
Cypress tips upgraded IDE for PSoC
Product News 8/21/2012 Post a comment
Cypress Semiconductor rolled out a new version of the PSoC 3 and PSoC 5 programmable system-on-chip development environment with more than 100 new features and enhancements.
How to simulate cable in SPICE
Design How-To 8/15/2012 1 comment
This article discusses the two main loss effects related to cables (the skin effect and dielectric losses) and presents a simple method for modeling the cable for use in standard SPICE simulators.
The forgotten SoC verification team
Design How-To 8/13/2012 4 comments
There is a growing class of verification engineers who are woefully under-appreciated in terms of the complexity of the job they have to do and the lack of tools made available to them…
ARM continues Synopsys EDA support
News & Analysis 8/10/2012 1 comment
Processor IP licensor ARM has said it continues to work with all the major EDA companies after being asked about claimed improvements in the design of ARM-based system-chips made using design tools from Cadence.
Wafer-scale CMOS X-ray imaging for medical apps
Design How-To 8/10/2012 Post a comment
There is a growing interest in the use of solid-state based X-ray medical imaging and detection systems in the replacement of conventional diagnostic imaging techniques. One of these technologies is wafer-scale CMOS sensor-based imaging, which can bring advantages in terms of performance such as high resolution, high dynamic range and low noise capabilities.
London Calling: Deutsche does M2M
Blog 8/10/2012 3 comments
Software development is a fast moving business. Before the Qt development framework is fully established Nokia has had to sell it on and the lure of the Internet of Things is exciting Deutsche Telekom.
Microelectronics Olympiad backed by Synopsys, IEEE
News & Analysis 8/9/2012 Post a comment
It won't be speed over 100-meters but knowledge about microelectronics at the nanometer-scale that will determine the winners in a competition to take place in Yerevan, the capital of Armenia, later this year. The idea behind the design games is to turn microelectronics engineers into medal winners and inspire the next generation to enter the electronics industry.
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