Currently, the most widely-used storage device is the Hard Disk Drive (HDD), but its popularity is rapidly declining.
HDD Verification and Validation
Verifying an HDD controller is a daunting task. The nature of its composition that combines analog and mixed-signal IP with traditional digital SoC and robust firmware necessitates a hierarchical, multi-stage methodology (Figure 3).
Figure 3. Hard disk drive hierarchical, multi-stage verification methodology (Click Here for a larger image. Source: Lauro Rizzatti)
The approach starts at the IP level performed by the IP vendors. The servo is verified via a SPICE simulator, although the complexity of the analog functions makes it difficult to accurately model its behavior in an overall system. As discussed later, they are tested at the system-level via in-circuit-emulation (ICE).
The verification of the hardware portion of the digital SoC is straightforward and like that of any other embedded design. Gate-level and register transfer level (RTL) simulation are used at the block level, driven by functional coverage until reaching virtually 100% coverage. It should be noted that, lately, formal verification methodologies are deployed as well.
Full SoC-level verification is performed in the context of system-level integration with the firmware.
Initially, RTL simulation is used at the system level, but the lack of performance power of RTL simulators limits the verification to basic and simple operations -- at most, one hundred or so read/write cycles between adjacent tracks. At this stage, the servo and analog functions are replaced with a simple model.
Thorough system-level integration and firmware validation requires the execution power of hardware-assisted verification engines in the form of hardware emulation and FPGA prototyping -- two critical items in the verification team's toolbox.
Hardware emulation provides the performance necessary to carry out vast amounts of clock cycles -- numbered in the hundreds of millions or even billions -- required for firmware execution. In this regard, FPGA prototyping is even more powerful in terms of processing clock cycles per second, but FPGA prototyping does not provide the debugging capabilities essential for tracing bugs in the hardware and firmware.
As mentioned earlier, the firmware is an integral part of the whole system, and changes to the firmware are considered at the same level as changes to the hardware. In fact, and contrary to conventional wisdom, engineering teams sometimes opt to fix a firmware bug by changing the affected hardware to avoid the risk of altering the operations of the HDD system.
FPGA prototyping and emulation coexist in the validation and verification methodology. FPGA prototyping is used for system validation, while emulation is used for tracking-down bugs.
In-Circuit-Emulation for HDD Verification and Validation
Today, hardware emulation can be used in one of two broad modes of deployment. In the traditional ICE mode, the design-under-test (DUT) mapped inside the emulator is physically connected to the real target system in place of the to-be-taped-out silicon chip. The physical target system sends stimuli and receives responses from the DUT. In a modern virtual mode -- devised and perfected over the past decade or so -- the DUT mapped inside the emulator is connected to a soft-model of a target system via a transactional interface that sends stimuli and receives responses from the DUT.
The difficulty in accurately modeling the analog portions of the HDD design favored the deployment of the emulation system in ICE mode. Verification engineers assemble all the HDD pieces, hard IP, and soft models for the SoC and debug the controller at the system level.
It should be noted that, as verification engineers move from the individual component to a full system, with multiple hardware components plus interacting with firmware, complexity grows exponentially. It is not uncommon to discover unforeseen sequences that only manifest themselves at the system-level as classic "corner-case" bugs.
Issues that must be addressed in verification include:
- Testing all host interface standards (SAS/SATA, USB 3.1).
- Security (FIPS) certification with third-party IP.
- Encrypted third-party IP debug at the system level.
- Power constraints.
A dilemma arises: if the IP were to be verified with every possible combination of the system configurations it would go into, the verification cost would be prohibitive and testing would take too long. Since HDD schedules are aggressive, companies are willing to take short cuts, get imperfect IP blocks, integrate them into the system, and then find bugs that are related to each specific system configuration. Once fixed, they ship the product. It's an economic trade-off that works... most of the time.
While the HDD is moving away from the leading position it enjoyed for two decades to be replaced by the SSD in everything from laptops to data centers, it will remain the leader in inexpensive, large-capacity devices for decades to come. The number of innovations and changes to the HDD technology is rather limited, making iterative changes relatively low-risk.
Will the HDD industry switch the use of hardware emulation from ICE to virtual and gain the benefits that come with this approach -- multi-use to remote access, essential attributes to deploy the emulator in a data center? We predict the answer is "no."
Engineers have been comfortable using the ICE approach for many years. They've gained invaluable experience, the approach works well, and the risks to fail associated with a change in verification methodology are too high.
As it happens, however, emulation deployed in virtual mode fits perfectly in the verification and validation methodology of SSD designs, which will be the topic of our next article.
Dr. Lauro Rizzatti is a verification consultant and industry expert on hardware emulation (www.rizzatti.com). Previously, Dr. Rizzatti held positions in management, product marketing, technical marketing, and engineering. He can be reached at email@example.com.
Ben Whitehead has been in the storage industry developing verification solutions for nearly 20 years. He has been with LSI Logic and Seagate, and has most recently managed SSD controller teams at Micron. His leadership with verification methodologies in storage technologies led him to his current position as a Storage Product Specialist at Mentor Graphics.