When using brown-out reset circuits, the bottom line is that on many MCUs you can't use the A/D to monitor Vdd during flash writes unless there's some way to simulate the expected load. As always, do a careful, worst-case engineering analysis.
Recently, I recommended against using the brown-out reset (BOR) circuit found on many MCUs. My argument was that BORs often have a wide tolerance range, which means one could give up nearly all of a coin cell's capacity. For instance, some are rated as triggering a reset at some nominal voltage, but the tolerance bands are 2.05 to 2.35 volts. Worst-case design means assuming it will fire at 2.35, which, with a decent load on the battery, means it may initiate a reset when there’s 90% or more of the battery’s capacity left.
Further, some BOR circuits use quite a bit of juice, in some cases too much to support years of (mostly sleeping) operation off a coin cell. I suggested, instead, waking up once in a while and reading Vdd with an A/D, and wrote that the load during this measurement must reflect the real, expected load while awake. I still think this is good advice. However, in some situations this solution might be impossible to implement.
The nice people at Microchip called to explain some of the scenarios they see their customers experiencing. One I hadn’t considered is writing to flash memory. This can suck some serious coulombs. On their PIC18LF46K22, writes can take 10 mA for around 6 ms/block (not an unusual number; TI’s MSP430F2013 needs 7 mA during flash erase). As the battery is slowly depleted its internal resistance may be low enough to run code, but so high that Vdd will drop below the minimum allowed during the flash write. The result: Who knows? With Vdd below the minimum the CPU needs, any internal register, like the program counter, could become corrupt.
Why not use the A/D to check Vdd during the flash write? Well, on some MCUs that’s quite impossible, since all instruction execution is suspended during the write. Perhaps it makes sense to turn the BOR on only when the processor is not sleeping, and let it issue a reset when writing to flash if the battery just isn’t able to power the system properly. However, if the BOR goes off at 2.35 volts, and flash writes eat 10 mA, then, assuming no other significant loads during the write, the BOR will signal battery failure when around 160 mAh have been consumed. That is, about 30% of the battery’s capacity will be wasted.
The blog continues on EE Times' sister site Embedded.com.