# Power Tip 74: Interleaving Gets More Power From a Flyback

**Robert Kollman, Senior Applications Manager, Texas Instruments**

8/18/2014 03:13 PM EDT

4 comments post a comment

In his final Power Tip, Robert Kollman looks at the number of benefits to be gained from interleaving a flyback power supply design.

The flyback is the work-horse of power supply topologies. It works quite well for a wide range of inputs, low to medium power levels, and high-voltage inputs and outputs. Semiconductor component count is low as there is only a primary switch and output rectifier. It is, however, power limited due to the high currents that it generates. Its usefulness is usually limited to less than 100 watts. Above this power level, designers start considering other topologies.

In high-power flybacks, the power dissipations in the semiconductors are high enough that single packages for each are no longer viable. Multiple parallel packages may be used, but balancing current to equalize the temperature becomes an issue.

Buck regulators use multiple phases to mitigate this issue. Power stages are repeated and the inputs and outputs have common connections. The phases are offset in time to provide capacitor ripple current cancellation and a higher effective switching frequency. This same technique can be employed with the flyback as shown in **Figure 1**. The top schematic shows the familiar flyback in its simplicity while the bottom schematic shows the interleaved design.

At first glance, the interleaved design has twice as many components. But when using this method, you generally will be delivering more power than a single package could sustain in the single-phase design, so the component count will be similar between the two.

On the chart to the right of the schematic we have the capacitor ripple currents, red for the single-phase design and blue for the interleaved. Ripple current in the single-phase design is positive when the power switch is on, and negative to recharge the capacitor when the switch is off. It is worst-case at 50% operation when the reset voltage on the transformer is equal to the input voltage. For the interleaved design, this is the best case. The two phases are drawing currents at 180° difference and the ripple currents completely cancel.

**Figure 2** shows the ripple current variation over a wide line range. These curves have been generated with the assumptions of 50% maximum duty factor and the reset voltage equal to the minimum line voltage. This figure has been normalized in a couple ways. The horizontal axis normalizes the input voltage by the reset voltage and shows a 4:1 line range indicative of a universal input.

The vertical axis normalizes the RMS current in the input capacitor divided by the DC input current at low-line (which in this assumption equals the reset voltage). As shown in the previous figure, the RMS input current for the single-phase design is worst case at a duty factor of 50%, which corresponds to an input voltage equal to the reset voltage (V_{IN}/V_{RESET}= 1).

At this condition in the two-phase design, the two power-stage currents cancel each other resulting in zero AC current in the input bypass capacitor. To establish ripple ratios between the two, the worst case single-phase ripple point is a normalized ratio of 1. For the two-phase, the worst ratio is about one third. In other words, if you were picking input capacitors based on ripple current rating, the two-phase design uses one third the capacitors of the single-phase design.

The output capacitor follows similarly if the capacitor is chosen based on ripple current alone. If it is chosen based on ripple voltage and equivalent series resistance (ESR), the two-phase design has half the peak-to-peak ripple current. Consequently, it produces the same ripple with half the capacitors.

**Figure 3** presents an interleaved flyback with a push/pull controller. This design has a rectified universal input voltage and produces about 150 watts of output power.

I thought the 36V/4A output was too much current for a single rectifier. Also I considered two in parallel, but decided that balancing the current would be a problem due the negative temperature coefficient of their junctions. In the end, I implemented the interleaved design using a current-mode, push/pull controller.

I sensed the individual phase currents with current sense resistors and combined the sense signals to provide a single input to the control circuit. Since the peak currents were roughly equal, the two power stage output powers were nearly equal, resulting in even heating of the power switches and rectifiers.

To summarize, interleaving a flyback offers a number of benefits. It reduces the ripple current in the input and output filter capacitors. This allows you to save cost by using fewer parts or to reduce the ripple voltage of the power supply. Plus, it raises the effective switching frequency of the power supply.

You can take advantage of this by reducing the frequency and thereby reducing switching losses or by running at the higher effective frequency and reducing the filtering. Interleaving also spreads the heat to make for better thermal management. Finally, it allows you to reduce transformer height since the transformer volume is determined by power.

Each transformer handles half the power, so its height should be 80% that of a single one (0.5^{1/3} = 0.8). On the downside, there will be two transformers in the interleaved design. And then there are all the extra components shown in **Figure 1**. However, there are also additional components in the single design to accommodate the higher power dissipation. On the plus side, if you use current-mode control for the interleaved design, you will get current matching, which tends to equalize dissipations in the MOSFETs and diodes.

Numerous interleaved flyback designs are available in PowerLab, including PMP5871 and PMP9063. While you are there, examine some of the 1,400 reference designs that we have built, tested, and documented for your use.

Check out TI Power Lab Notes for a designer's prospective on his power supply designs.

Here's more information about this and other power solutions from TI.

For all previous Power Tips articles, see the Power Tips Index.

All good things have to come to a close, as does my stint as a power supply engineer at Texas Instruments. I will be retiring to the Caribbean aboard my boat "Power Play" in August. I want to thank my readers for their attention during the past six years and want to encourage their continued participation in the fun world of power electronics. It has been a very rewarding career for me. As they say about power supplies, everybody has one and they don't generally like to talk about it.

Author

pawanapt 8/22/2014 5:44:43 AM

We have made prototypes and I am looking for some theroritical studies or will do some theoritical calculations where the ripple current of the said bulk elco can be calculated with variation of the duty cycles of both stages .

Further I am even thinking of using SG3524/3525 for the interleaving stages.

TI- delhi team is aware of the project.

Regards,

Pawan Bothra.

pawanapt@hotmail.com.

Author

green_is_now 8/21/2014 3:05:47 PM

further down the refinement onion...

When the duty cycle is exactly 50% and the ramp slope going up and down is exactly the same the ripple cancels and aproaches zero!

minus the edge spikes, dead time, edge jitter...but these are an order of magnitude smaller problems than bulk ripple.

But power supplies don't operate at this point, but can be tailored for a specific sweet spot where a supply typically operates.

If your system can tolerate more ripple outside the sweet spot your done. If not, then something else needs to be done.

And ripple specs are worst case across the load range.

Perhaps a layered article that builds on this one can go into the benifits of N phase interleaving and how it helps and the deminishing returns of adding more than 3 or 4 interleaved sections provide.

Also some insight into how big or small a problem of variable ripple% is over load can be would be useful. Comparing 2 phase with 3 phase over load would be a great example to raise understanding.

Also how dynamic voltage scalling can buy some headroom for ripple issues, especially at low load to high load transition points where the extra voltage headroom has limited impact, as both ripple and ramp response determine brownout and overvoltage failure points, with and without dynamic proactive voltage scalling also has a lot of value toward cleaner and more efficient SMPS design.

Author

rich.pell 8/20/2014 10:17:42 AM

Author

Ryszard.Milewicz 8/19/2014 5:37:03 PM

thank you very much for all tips, ideas and suggestions, which can be used in everyday design work. All the best!