Automotive SoCs at ISSCC showed designs that were more aggressive in some ways than their counterparts for mobile phones and notebook computers.
Car SoCs are not exactly leaving mobile chips in the dust. It’s worth noting only a handful of chips made in 14/16nm FinFET processes are shipping today, mainly Apple and Samsung smartphone apps processors with Qualcomm’s Snapdragon ramping up on deck.
MediaTek’s latest smartphone app processor, described in the ISSCC session, was no slouch. It integrated eight Cortex-A53 and two A57 cores as well as GPU, modem and media subsystems.
The 20nm chip organized the cores into three clusters, creating a novel Big.Little and medium arrangement. The middle 2 GHz cluster of A53s staked out a unique ground, providing 40% more performance than the low-end 1.4 GHz A53 cluster and 40% more power efficiency than the high-end 2.5 GHz A72 cluster.
Given their small die size, there’s no limit in sight to how many cores you might pack on a mobile SoC, Uming Ko, vice president of technology at MediaTek told me. “If you create a straight line between ultra-low power and high performance and enough performance points along it you can continue to find efficiencies from adding more cores,” he said.
MediaTek used a 20nm process for its apps processor that is now shipping.
For its part, AMD engineers showed smart ways of squeezing as much as 15% more performance out of its Carrizo PC processor, simply by applying more aggressive power management to the 28nm design. The Bristol Ridge design was a study in using power management to overcome performance limits tied to heat, voltage and current.
Separately, I asked the Renesas engineers about their experiences with the 16nm node where SoCs need to negotiate multi-patterning and FinFETs. The chip architects are somewhat removed from those implementation challenges, but they had some opinions.
“There are many trials and difficulties with 16nm…power consumption is a problem, sometimes reliability is a problem,” said Takahashi. Memory cells are very compact [at 16nm] and memory lines are short and thus more susceptible to software errors, he added.
Foundries provide 16nm interconnects, but they lack support for advanced features such as quality-of-service controls that Renesas builds into its own on-chip interconnects, Takahasi said. To ease design and verification jobs at 16nm, some Renesas teams still use Verilog and need to upgrade to higher-level design languages such as System C which is already in use by some teams at Renesas.
The relatively high frequency clocks used at 16nm make it hard to keep power consumption low, said Mochizuki. The 16 nm node “is less flexible compared to previous processes…we may [need to] change the [design] style [we use] for low power,” he said.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times