In a recent discussion about the necessary differences between tools for ASIC developers as compared to the needs of FPGA users, one expert called it 'a dumbing down,' but guest blogger Brian Bailey says 'that is just wrong.'
Max has asked me to contribute a regular guest blog to his Programmable Logic Designline, and I am delighted to be able to do that. Those who know me will be expecting to hear lots about verification, and that is true. I will be concentrating on two aspects in this area – firstly the use of programmable logic to verify a design that may be intended for implementation in an ASIC and secondly, the verification of a design that is destined for implementation in programmable logic.
This latter case also includes issues such as debugging, instrumentation and in-circuit monitoring. The other area of particular interest to me is ESL, and programmable logic has a big role to play here. Not only are there tools emerging that concentrate on going from high levels of abstraction to FPGAs, but in addition many of the most advanced SoCs are a combination of both fixed function configurable logic and some fully programmable components. In fact, I predict that many of the largest chips in the future will have some amount of programmable logic on them for customization purposes. The ESL tools that are already being developed for some of these chips are quite advanced. If you have products, methodologies or ideas that you would like me to blog about in these areas then please drop me a line at firstname.lastname@example.org
So for this my first blog here, I would like to pick up on a discussion that I blogged about a little earlier that week. It was my reaction to a discussion from various experts in the verification field. Part of that discussion talked about the necessary differences between tools for ASIC developers as compared to the needs of FPGA users. One of those experts called it "a dumbing down" – but that is just wrong. It is true that FPGA users do not always need all of the same flexibility as an ASIC developer because of the structure or rigidity of the implementation architecture, and it is also true that many FPGA implementers may not have the same level of expertise in designing hardware. What this does is to create different needs and for tools that can get the job done with the minimum level of interaction from the user. In many cases this actually requires a more intelligent tool than that offered to the ASIC developer.
As an example consider the FPGA synthesis solution developed by Synplicity. Is this a dumb synthesis tool? Absolutely not – it was a highly sophisticated tool that did a better job than most of the other synthesis tools on the market when targeting an FPGA, and it did it without the 1000s of options and configurations needed to get results from many of those other tools. It presented a simpler user interface to the user and that enabled him to get a good job done. This is very similar to the approach taken by Apple when developing consumer products. Are Apple devices dumb? No – just because they have simplified the way their devices operate does not make them dumb – it makes them the most usable and successful devices in all of the areas that they have tackled, and in my book that makes them the most advanced products. Apple managed to do this by using innovations way ahead of the wannabe device creators.
Brian Bailey – keeping you covered!