# FPGAs: System gates or logic cells/elements?

This is one of those questions that keeps on coming back to bite us. May 1,000 curses rain down on the heads of those marketing weenies who first came up with the concept of *System Gates*

Arrgghhh! Will this never end? I just received an email from someone who asked:

*Hello Max, Would you please provide me any details about relation between Logic Elements (LEs) and System Gates count. What would be the count of LEs equivalent to 230K system gates in FPGAs and CPLDs. In most of Altera’s product datasheets only LEs are mentioned, but not system gates – is the present FPGA emphasis more on LEs instead of system gates?
*

OK, here we go… In the ASIC world it’s common to talk about “equivalent gates.” The idea is to convert each logic function in an ASIC design (multiplexer, register, whatever) into some number of equivalent gates – say 2-input NAND gates – and then add them all together to say “This design has XXX equivalent gates.” This provides a way to compare different ASICs so that one can say “Ha! Mine is bigger than yours (and so is my ASIC)!”

Note:As an aside, you may also be interested in my articleWhat's the number of ASIC versus FPGA design starts?(Click Hereto see that article).

Early FPGAs predominantly consisted of programmable fabric in the form of “islands” of logic [called logic cells (LCs) by some and logic elements (LEs) by others] floating in a “sea” of programmable interconnect. Each LC/LE was formed from one or more look-up tables (LUTs) coupled with some additional logic like one or more register bits and one or more multiplexers.

Each LUT could be used to represent a function that would be the equivalent to some number of equivalent gates. For example, someone once told me that a 4-input LUT could be used to represent functions that were the equivalent of anywhere between 1 and 20+ regular logic gates.

Problems arose when people wished to compare ASICs and FPGAs. For example, if someone had an existing ASIC design that contained 500,000 equivalent gates and they wished to migrate this design into an FPGA, how could they tell if their design would “fit” into a particular FPGA?

In order to address this issue, in the early 1990s, FPGA vendors started talking about “System Gates” Some folks say that this was a noble attempt to use terminology that ASIC designers could relate to, while others believe it was purely a callow marketing ploy that didn’t do anyone any favors.

The idea was that each system gate was the equivalent to some number of regular logic gates. Now, the FPGA vendor could proudly say “our FPGA can implement XXX system gates,” then somewhere in the fine-print they would say

*“One system gate is equivalent to YYY logic gates.”*

But things are never simple, because even assuming that one was talking about an FPGA containing only rudimentary programmable fabric, it would be difficult to state with certainly whether or not a particular ASIC design containing XXX equivalent gates could fit into an FPGA containing YYY system gates. This was because some ASIC designs might be predominately combinatorial, while others might make excessively heavy use of registers. In both cases, this could result in a sub-optimal mapping into the FPGA.

And things became even more complicated if an FPGA vendor went through an intermediate step of equating system gates to LCs/LEs – not the least that different FPGA architectures might boast LCs/LEs with different numbers of LUTs, and the LUTs themselves could have different numbers of inputs. The end result was that a system gate from one FPGA vendor might represent a radically different number of equivalent gates as compared to a system gate from another vendor.

And then things started to become complicated (grin), because today’s FPGAs don’t just contain programmable logic – they also contain hard macros and blocks of memory. In the case of hard macros like the Cortex-M3 microcontroller in Actel’s SmartFusion devices, for example, it’s common to say things like

*“This core is the equivalent to 10 million gates”.*

In the case of blocks of memory, it’s best to just think about these in terms of kilo/mega bits and/or bytes – as far as I’m concerned it really makes no sense to consider these blocks in terms of equivalent gates (actually there is an exception to this, but let's not go there...).

With regard to the programmable logic fabric itself – I don’t have a clue. Each FPGA will boast some number of LCs/LEs. Each of these LCs/LEs will contain some number of LUTs. Each of these LUTs may have anywhere from 3 to 8 inputs depending on the FPGA architecture.

So... the end result (as far as I’m concerned) is that it’s really meaningless to think in terms of system gates and/or equivalent gates in the context of FPGAs. Now that FPGA designs have become so pervasive, I think it’s much simpler to think in terms of the total number of LCs/LEs in a device, and to then think of the various large functional blocks in the design in terms of the number of LCs/LEs they consume (remembering that a LC/LE in one FPGA may be radically different to a LC/LE in another FPGA).

Of course I might be wrong (grin). What do you think? Do you agree with the above or would you augment / modify my description in any way?

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Max The Magnificent 11/16/2010 5:44:00 PM

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jangray 11/16/2010 6:14:04 PM

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DrFPGA 11/22/2010 5:25:06 AM

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SZA 3/25/2011 3:42:15 PM

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SZA 3/25/2011 3:49:00 PM

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Willson 9/30/2011 12:37:53 AM

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Max The Magnificent 9/30/2011 3:06:51 PM

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edastech 6/4/2014 1:03:04 AM

of comparison Xilinx gives gate count information for thr FPGA

devices while selecting the capacity of logic for the same and here

starts the confusion when comparing with other vendors like Altera