EDA vendor will pay about $380 million to acquire dataplane processing IP firm.
Well, I certainly wasn't expecting this, but it does make a lot of sense.
The folks at Cadence have all sorts of cool technology when it comes to designing and verifying ASICs, ASSPs, and SoCs, including an extensive library of intellectual property (IP) cores.
Meanwhile, the guys and gals at Tensilica have some real cool technology with regard to creating IP cores for use in ASIC, ASSP, and SoC designs in the form of their dataplane processing units (DPUs).
Tensilica's flagship product are Xtensa Customizable Processors. Users can customize Xtensa DPUs to act like anything from a small, low-power cache-less controller to a high-performance 16-way SIMD, 3-issue VLIW DSP core. As they say on their website:
You can make Xtensa processors uniquely your own in two basic ways:
- Configurability: Xtensa offers a menu of checkbox and drop-down options so that you can pick just the features you need. Once you've determined the best implementation, our automated Xtensa Processor Generator creates, in a matter of minutes, pre-verified RTL and a complete matching software toolchain, including models for system integration and EDA scripts for production.
- Extensibility: Add your own instructions, registers, register files, and much more using the Tensilica Instruction Extension (TIE) methodology. The designer only has to specify the functional behavior of the new data path elements in the TIE language (Verilog-like) and then the RTL and whole tool chain is automatically generated.
Furthermore, in addition to creating pre-verified RTL, the Xtensa Processor Generator
also generates a complete software tool chain, including a compiler, debugger, instruction set simulator, profiler, power estimator, system models, EDA tool scripts and more. This development tool chain is automatically adapted to all options and any custom extensions.
On top of all this, the folks at Tensilica have used this technology to create a suite of "off-the-shelf" cores called the Diamond Standard
So, as I say, Cadence acquiring Tensilica makes a lot of sense – it's just that I wasn't expecting it. The official release (with all the boring bits) is as follows:
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that it has entered into a definitive agreement to acquire Tensilica, Inc., a leader in dataplane processing IP, for approximately $380 million in cash. Tensilica had approximately $30 million of cash as of December 31, 2012.
Further expanding Cadence's IP portfolio, Tensilica provides configurable dataplane processing units that are optimized for embedded data and signal processing targeted at mobile wireless, network infrastructure, auto infotainment and home applications.
"With Tensilica, we will be able to provide designers with a more complete SoC solution that will speed the development of innovative and differentiated products, while reducing time to market," said Lip-Bu Tan, president and chief executive officer of Cadence. "We look forward to working with Tensilica's dedicated employees as one team to bring even more value to our customers."
Jack Guedj, president and chief executive officer of Tensilica stated, "Joining Cadence will provide a broader platform to expedite our product development strategy and customer engagement. We will have the ability to accelerate IP subsystem development and integration while providing a more extensive support network to our customers."
Tensilica customized DPUs augment traditional custom hardware design, offering both time-to-market and programmability advantages and can be optimized to achieve optimal power, performance and area efficiency. Tensilica IP provides application-optimized subsystems that work synergistically with industry-standard CPU architectures.
"The acquisition of Tensilica by Cadence will be a positive move for the industry," said Simon Segars, president of ARM Holdings plc. "We look forward to expanding our ongoing collaboration with Cadence to enable our customers to bring great products to market."
Cadence intends to finance the transaction with available cash and an existing revolving credit facility. The transaction is expected to close in the second quarter of fiscal 2013, subject to customary closing conditions including regulatory approvals. Cadence expects the transaction to be slightly dilutive to its non-GAAP earnings per share in fiscal 2013 due to the impact of merger-related accounting and accretive to its non-GAAP earnings per share in fiscal 2014. The impact on GAAP earnings per share will be available after valuation and the completion of purchase accounting.
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