Jasper and Duolog are creating integrated design and verification flows that tackle some of the toughest problems associated with integrating hundreds of IPs into an SoC...
Life as a small EDA company has, until recently, been about doing something better than the big 3, or by finding some function that is complementary to what they do, and then integrating into their flows. This appears to be changing in that more of the smaller EDA companies are now choosing to partner with each other to create sub-flows that can have a real impact on their own. This week, we see another example of this where Jasper Design Automation and Duolog Technologies have come together to create integrated solutions that will address the SoC integration and verification problem – an area that has remained essentially ignored by the big EDA companies.
Chips these days may contain hundreds of unique IP blocks, with many of them having several instantiations in different configurations. Just as in the past we would not have expected a circuit to work, just because the individual gates are known to work, there has been an almost tacit acceptance that if IP blocks work, then it just stands to reason that the whole SoC will work. Companies are quickly finding that this is not true and are desperate for tools that help solve this problem.
The integrated Duolog and Jasper tools and flows will enable design teams to identify issues, inconsistencies and omissions when assembling complex IP-based systems. The integrated design flows enable designers to work from black-box system specifications, through design capture and integration, to verification. Teams can verify the correctness of both the specification and the implementation, while also detecting gaps in the specification.
The partnership will initially deliver two flows. The first will focus on the capture and verification of register metadata, combining Duolog’s Socrates Bitwise register management tool with the JasperGold® Control and Status Register (JG-CSR) Verification App. The flow will enable IP designers to verify both executable specifications and RTL for consistency and completeness.
The second flow leverages Duolog’s Socrates Weaver SoC integration tool and the JasperGold Connectivity Verification App (JG-CONN). This flow will enable SoC design teams to assemble, construct and exhaustively verify a complete SoC integration, including temporal and conditional connections, as well as multiplexed IO connections.
Duolog’s and Jasper’s solutions utilize the IEEE1685 IP-XACT standard as a robust data exchange format to seamlessly exchange metadata among the different tools and enable these joint flows.
Also, if you weren’t aware, ARM IP is being packaged using IP-XACT which means that these solutions are 100% interoperable with ARM IP enabling a fully automated methodology and flow.Brian Bailey
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