I've taken a look at the sessions and picked out a few that I think are worth a closer look for designers working with memory.
ESC Boston is coming up this September 26-29 at the Hynes Convention Center. There are many tracks available, as ESC Boston combines with DesignCon East, DesignMED, and Designing with LEDs. You can check out full show details here.
I've taken a look at the sessions and picked out a few that I think are worth a closer look for designers working with memory. If you are going to be at the show and attend one or more of these, please post comments on what you think. Also, if you will be at the show and think Memory Designline readers might be interested in other events there, please hit the comments as well.
Session Number: DCE-203 Tools and Techniques for Debugging DRAM Memory Speaker/s: Ken Price (Product Planner, Performance Oscilloscopes, Tektronix) ?Date / Time: Tuesday 10:30-11:45 ? Today’s memory systems are becoming faster, making performance verification extremely difficult. DDR signals in particular can present unique challenges, due to the intermittent nature of the read/write bursts, presenting the need for measurements to sometimes isolate signals from one rank within a mixed data stream, and other unique characteristics. This session will review several approaches for using advanced triggering and/or search functions in a test environment that can enable the test engineer to pinpoint the exact signal conditions or patterns of interest, necessary for successful debug of today’s faster DDR DRAM systems.
Session Number: SS-233 Hands-on Seminar with Micron Phase Change Memory Speaker/s: Yuliya Shlemenzon (Product Marketing Engineer, Micron Technology) and Todd Legler (Senior Applications Engineer, Micron Technology) ? Date / Time: Tuesday 12:00- 1:15 and Tuesday 3:00- 4:15? PCM is revolutionizing the way memory subsystems are designed. This session will focus on hands-on interaction with Micron PCM device using a reference board. We’ll begin by introducing Micron PCM technology and products. Attendees will collect performance data on both NOR and PCM to learn how eliminating the erase operation improves system performance and simplifies software. You’ll learn how high endurance of Micron PCM can simplify memory subsystem.
Session Number: SS-234 Optimizing Your Memory Subsystem Speaker/s: Bill Stafford (Marketing Director, Micron Technology) ? Date / Time: Tuesday 1:30- 2:45 ?In today’s uncertain economy, it is critical to incorporate flexible design practices and choose the right combination of memory devices for the life of your platform. Keeping up with NOR, NAND, and DRAM trends is the key to a solid memory solution. Design practices should seek to balance maximum performance while minimize total system costs for a reliable memory-subsystem. As a comprehensive, knowledgeable provider with the most extensive portfolio of industrial NVM and specialty DRAM products, Micron can guide you through the steps to simplify the memory-selection process.
A 5G interoperability test system developed by Qualcomm, ZTE and China Mobile, combined with the pending development of the first 3GPP 5G-NR standard, are good indicators of the pending frenzy over 5G; it’s a good time to take a Boot Camp course on 5G.