We review the main underlying concepts of micropipelines before deploying them in real FPGAs.
The micropipeline is a powerful yet simple design approach allowing the implementation of extremely efficient asynchronous circuits. In this blog, we will review the underlying concepts of micropipelines. In future columns, we will deploy them in real FPGAs.
Editor's Note: This article first appeared on All Programmable Planet, which was a thriving community website devoted to all things programmable. Sadly, the site is no longer with us, but many friendships forged there will last for years to come.
Ivan Sutherland introduced the term "micropipeline" in a 1988 Turing Award Lecture. Sutherland is widely regarded as the father of computer graphics. During his prolific career, he has received a plethora of honors and prizes. For the past few years, he has devoted himself to developing VLSI processing architectures, with a special emphasis on asynchronous logic. Since stepping down as fellow and vice president at Sun Microsystems, he has been leading the research at Portland State University's Asynchronous Research Center.
Dr. Ivan Sutherland.
Before we delve deeper into the micropipeline concept, let's set the scene with some useful definitions. This will let us classify any pipeline structure, including micropipelines.
- Clock discipline: Pipelines can be clocked or event-driven, depending on whether their parts respond to a widely distributed clock or act independently when local events permit. That's why we can call them synchronous or asynchronous, respectively.
- Data load: Some pipelines are inelastic, because the amount of data in them is fixed. In the case of inelastic pipelines, the input and output data rate must be the same. Other pipelines are elastic; the amount of data in them may vary. The input and output rates of an elastic pipeline may vary and differ momentarily due to internal buffering.
Once we understand these definitions, we can define a micropipeline as a very simple form of event-driven, elastic pipeline -- with or without internal processing. As Sutherland said in his lecture: "The micro part of this name seems appropriate to me because micropipelines contain very simple circuitry, because micropipelines are useful in very short lengths, and because micropipelines are suitable for layout in microelectronic form."
Depending on whether micropipelines include internal processing or not, they can be used in different roles throughout a hardware system. Without internal processing, the micropipeline becomes an elastic FIFO and can be used to connect unaligned clock domains or to build buffers in packet processing applications. With internal processing, micropipelines may be used to build general pipelined processing architectures, such as whole asynchronous RISC processors, complex memory interfaces, or DSP engines.
By using a mixture of micropipelines with and without internal processing, asynchronous network-on-chip architectures can be easily deployed. In this way, micropipelines are a key building block in the design of advanced globally asynchronous, locally synchronous (GALS) systems, which offer one of the most promising ways to overcome the clocking issues seen in today's deep-submicron SoCs.
Now that we have formally defined what micropipelines are, let's consider their behavior and potential advantages.
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