The move to 20nm bulk CMOS and 16/14nm FinFETs brings one of the most serious challenges the semiconductor industry has faced in 20 years.
The semiconductor industry's growth has historically depended on a reduction in cost per transistor with each migration to smaller dimensions, but next-generation chips will not deliver this cost reduction. The impact of this situation is one of the most serious challenges the industry has faced within the last 20-30 years.
Specifically, next-generation 20nm bulk high-K metal gate CMOS and 16/14nm FinFET process will deliver smaller transistors. However, they will also have a higher cost per gate than today's 28nm bulk HKMG CMOS (below).
IBS initially projected the increase in cost per gate in 2011.
The cost problem stems in part from difficulties obtaining high parametric yields and low defect density at the new nodes.
The 20nm node faces difficulty achieving low leakage due to challenges in controlling doping uniformity, line edge roughness, and other physical parameters that are very sensitive to minor variations in manufacturing processes. The need for double patterning at 20nm also adds cost per wafer over 28nm.
The 16/14nm FinFET node uses the same interconnect structure as 20nm, so the chip area is only 8-10% smaller than 20nm. In addition, this node faces yield issues related to stress control, overlay, and factors related to the step coverage and process uniformity of 3D structures.
The cost problems will persist because, as 28nm bulk CMOS matures, wafer depreciation costs will drop 60-70% from the rampup and initial high-volume phase. As a result, the cost per gate for 28nm bulk HKMG CMOS will be much lower than FinFETs even in the fourth quarter of 2017. A similar pattern will occur for 20nm HKMG in 2018 or 2019 when depreciation costs decline.
The data indicates that FinFETs can be used for high-performance or ultra-dense designs but are not cost effective in mainstream semiconductors. Consequently, the industry faces a mismatch between what is being promoted by wafer vendors and what their customers need.
There's no end in sight for this situation. Scaling to 10nm and 7nm nodes will entail additional wafer processing challenges for which the industry is not well prepared.
Next page: Exploring the options