A new class of micro-gateways is emerging to increase performance and lower power consumption, driven by advances in FDSOI process technology.
Many Internet of Things applications envisioned so far include a system comprising a wireless or wired sensor network associated with a hub for gathering, processing, and storing information from the sensors. Local hubs, sometimes called micro-gateways, also will be needed.
Micro-gateways will ensure security and privacy, performance -- which sometimes requires low-latency -- and energy savings, given the power hungry nature of Internet transfers. These lightweight web servers will be able to retrieve information, store content, and perform some complex searching tasks like classic servers, but they will have to be inexpensive and able to perform those tasks on ultra-low power.
These local hubs can be seen as low-cost servers with performance equivalent to a five-year-old technology but with a huge reduction in power consumption. Micro-gateways may contain family databases with photos, videos, and personal data accessible only to selected friends and family with a high level of security.
To achieve their low-power objectives, micro-gateways will need accelerators for processing video or indexing and retrieving information. As a result, pure processor performance will not be the major issue, enabling simpler architectures with lower frequencies.
FDSOI process technology offers significant advantages for these IoT uses. It offers an ultra-wide voltage range, thanks to an adapted forward body bias applied on the SOI substrate. For example, the FRISBEE DSP demonstrated this year at the International Solid-State Circuits Conference can reach a performance up to 2.5 GHz at 1.3 V, while still demonstrating 460 MHz @ 400 mV, its most energy-efficiency point.
FDSOI technology also offers significant advantages through a strong reverse body bias that can cut off the leakage in sensor nodes by a factor of at least 10, as demonstrated by STMicroelectronics. New memory structures can offer 10x better energy efficiency, as demonstrated at the European Solid-State Circuits Conference in 2013.
Looking forward, Leti is currently working on an ultra-low-power computing node called LIoT with an objective of 10x better energy efficiency and 10x less leakage than previous state-of-the-art solutions. These results will be achieved thanks to a new approach, mixing sense-and-react operation for both RF and digital blocks, ultra-low-power non-volatile memories, and use of neural networks and asynchronous techniques.
— Fabien Clermidy is head of the digital design laboratory at CEA-Leti, a microelectronics research institute in France. Denis Dutoit and Edith Beigné also contributed to this article.