Using Menta's technology -- which is front-ended by Verific's parsers -- you can generate FPGA IP cores for use in your SoC designs.
A few days ago, Menta of Montpellier, France, announced that it had selected IEEE-compliant Verilog, SystemVerilog, and VHDL parsers from Verific to serve as the front-end to Menta's Origami Designer and Origami Programmer tools used to create embedded FPGAs for SoC designs.
On the one hand, this isn't too surprising. Every FPGA company on the planet -- Achronix, Altera, Lattice Semiconductor, Microsemi, Tabula, and Xilinx -- uses Verific's industry-standard Verilog, SystemVerilog, and VHDL parsers. What would be surprising and newsworthy would be if Menta didn't use Verific (LOL).
The more interesting story is that Menta appears to be experiencing a very successful business model selling compiled FPGA fabric IP to SoC designers. Let's take this from the top. There are tremendous advantages to creating a product that can be programmed (configured) to perform different tasks. The two forms of programmability are software-based and hardware-based.
Software-based programmability -- which is generally sequential in nature -- predominantly involves the use of microprocessors (MPUs), microcontrollers (MCUs), and digital signal processors (DSPs). By comparison, hardware-based programmability -- which is generally parallel in nature -- predominantly involves the use of field-programmable gate arrays (FPGAs). In both cases there are off-the-shelf and embedded solutions available.
In the case of off-the-shelf MPU, MCU, and DSP chips, you can purchase these little scamps from AMD, Atmel, Freescale, Infineon, Intel, Microchip, Renesas, Silicon Labs, Spansion, STMicro, Texas Instruments (TI), and XMOS to name but a few off the top of my head. If you are designing an SoC into which you wish to embed one or more MPU, MCU, and/or DSP IP cores, then the vendors of these IP cores include players like ARM, CEVA, Digital Core Design (DCD), Imagination (MIPS), and so forth.
In the case of FPGAs, off-the-shelf solutions can be obtained from companies like Achronix, Altera, Atmel, Lattice Semiconductor, Microsemi, Tabula, and Xilinx. But what do you do if you wish to embed FPGA fabric as an IP core in your SoC design? There have been a few offerings in the past, but most of these have faded into the sunset. One notable exception is Menta with its eFPGA IP core technology.
This is a compiled technology, which means you start off by specifying what you require, and then Menta's tools generate the corresponding IP core that you integrate into your SoC. A high-level view of a possible eFPGA core is illustrated below:
In this case, an eLB refers to an embedded logic block, an eCB is a hard custom block, and an eMB is a hard memory block. Using Menta's tool suite, you can configure the size of your lookup tables (LUTs) and the number of LUTs in each eLB. You can specify the number or eLBs, the number and types of eCBs (which can represent things like DSP functions), the number and sizes of the memory blocks, the number of input/outputs (I/Os), and even the shape of the eFPGA in the layout (square or rectangular).
So, where does Verific fit into all of this? Well, in two places actually. At the front-end of the design flow we have Menta's Origami Designer, which is a graphical interface that lets you capture the requirements specification for your eFPGA as illustrated below:
Now, suppose you have the RTL (Verilog, SystemVerilog, VHDL) versions of a number of functions that you might wish to implement in your eFPGA. In this case, Origami Designer can employ Verific's parsers to analyze this RTL and then play "what-if" games with different eFPGA architectures, including area, timing, and power estimations based on your selected SoC process technology.
Once you've captured your desired eFPGA architecture using Origami Designer, you then use Origami Generator to compile your custom eFPGA core. In the fullness of time, when you have the physical SoC in front of you, you will take the RTL (Verilog, SystemVerilog, VHDL) versions of the functions you wish to implement in your eFPGA and run them through Menta's Origami Programmer -- which is front-ended by Verific's parsers -- to generate the configuration file you will use to program the eFPGA fabric on your SoC.
I personally am tremendously enthused by this concept. I think embedding FPGA fabric on SoCs is something we will see more and more of in the coming years. What do you think about all of this?
— Max Maxfield, Editor of All Things Fun & Interesting