Just as Linux has become the standard OS for most computing devices, Berkeley researchers envision RISC-V becoming the standard ISA for all computing devices.
The case for an open ISA
Systems-on-a-chip (SoCs), where the processors and caches are a small part of the chip, are becoming ubiquitous. Thus many more companies today are making chips that include processors than in the past. Given that the industry has been revolutionized by open standards and open-source software -- like TCP/IP and Linux -- why is one of the most important interfaces proprietary?
While instruction set architectures (ISAs) may be proprietary for historical or business reasons, there is no good technical reason for the lack of free, open ISAs.
It's not an error of omission. Companies with successful ISAs like ARM, IBM, Intel, and MIPS have patents on quirks of their ISAs, which prevent others from using them without licenses that academia and many small companies can't afford. Even IBM's OpenPower is an oxymoron; you must pay IBM to use its ISA.
An ARM license doesn't even let you design an ARM core; you just get to use its designs. (Only about 10 big companies have licenses that allow them to design custom versions of ARM cores.) While the business is sound, licenses stifle competition and innovation by stopping many from designing and sharing their ISA-compatible cores.
Nor is it because the companies do most of the software development. Despite the value of the software ecosystems that grow around popular ISAs, outsiders build almost all of their software.
Neither do companies exclusively have the experience needed to design a competent ISA. While it's a lot of work, many today can design ISAs.
Nor are the most popular ISAs wonderful ISAs. ARM and 80x86 aren't considered ISA exemplars.
Neither can only companies that design ISAs verify them. Long ago, open organizations developed mechanisms to ensure compatibility with hardware standards, such as floating point units (IEEE 754), networking chips and switches (Ethernet), and I/O buses (PCIe). If not for such organizations, open IT standards would not be so popular.
Finally, proprietary ISAs are not guaranteed to last. If a company dies, it takes its ISAs with it. Digital Equipment's demise also terminated the Alpha and VAX ISAs. Note that an ISA is really an interface specification, and not an implementation.
There are three types of ISA implementations:
- Private closed-source, analogous to Apple iOS
- Licensed open-source, like Wind River VxWorks
- Free, open-source that users can change and share, like Linux
Proprietary ISAs in practice allow the first two types of cores, but you need a free, open ISA to enable all three.
We conclude that the industry would benefit from viable, freely open ISAs just as it has benefited from freely open versions of the software stack. For example, it would enable a real, free, open market of processor designs, which patents on ISA quirks prevent. This could lead to:
- Greater innovation via free-market competition from many more designers, including open vs. proprietary implementations of the ISA.
- Shared, open core designs, which would mean shorter time to market, lower cost due reuse, fewer errors given many more eyeballs, and transparency that would make it hard, for example, for government agencies to add secret trap doors.
- Affordable processors for more devices, which would help expand the Internet of Things, whose target cost could be only $1.
Next page: The case for RISC-V
The case for RISC-V
For an ISA to be embraced by an open-source community, we believe it needs a proven commercial record. The first question, then, is: Which style of ISA has a history of success?
There hasn't been a successful stack ISA in 30 years. Except for parts of the DSP market, VLIWs have failed: Multiflow went belly up, and Itanium was a bust despite billions of dollars invested by HP and Intel. It's been decades since any new CISC ISA has been successful. The surviving CISCs translate from complex ISAs to easier-to-execute ISAs, which makes great sense for crafting a valuable legacy code base.
A new ISA by definition won't have any legacy code, so the extra hardware cost and energy cost of translation are hard to justify: Why not just use an easy-to-execute ISA in the first place? RISC-style load-store ISAs date back at least 50 years to Seymour Cray's CDC 6600. While the 80x86 won the PC wars, RISC dominates the tablets and smartphones of the post-PC era; in 2013 more than 10 billion ARM-based SoCs shipped, compared to 0.3 billion 80x86 chips.
Given ISAs can live for decades, we project the future technological landscape to see what features might be important for a RISC-based, free, open ISA. Three platforms will likely dominate: IoT, personal mobile devices, and Warehouse-Scale Computers (WSCs). This landscape suggests four critical requirements:
- Base-plus-extension ISA. To match the needs of SoCs while maintaining a stable software base, a free, open ISA should have:
This is in line with today's practice of SoCs often using custom application-specific accelerators.
- A small core set of instructions that compilers and operating systems can depend upon
- Standard but optional extensions for common ISA additions to help customize the SoC to the application
- Space for entirely new opcodes to invoke the application-specific accelerators
- Compact instruction set encoding. Smaller code is desirable given the cost sensitivity of the IoT and the resulting desire for smaller memory.
- Quadruple-precision (QP) as well as single- and double-precision floating point. Some applications running in WSCs today process such large datasets that they already rely on software libraries for QP arithmetic.
- 128-bit addressing as well as 32-bit and 64-bit. The limited memory size of nodes on the IoT means 32-bit addressing will be important for decades to come, while 64-bit addressing is the de facto standard in anything larger. Although the WSC industry won't need 2128 bytes, it's plausible that within a decade WSCs might need more than 264 bytes (16 exabytes) to address all of their solid-state, non-volatile storage.
It takes years to get the details right, so it seems wiser to start with an existing ISA than to form committees and start from scratch. RISC ISAs tend to be similar, so many might be good candidates. The good news is that there are already three open-source RISC ISAs: SPARC, OpenRISC, and RISC-V.
Only RISC-V meets all four above requirements (see table below). RISC-V is also 10 to 20 years younger, so we could learn from and fix the mistakes of previous RISC ISAs -- e.g., SPARC and OpenRISC have delayed branches -- which is why RISC-V is so simple and clean. In addition, the 64-bit address version of SPARC (V9) is proprietary, and OpenRISC may have lost momentum.
RISC-V surpasses other options for a free, open ISA.
RISC-V has plenty of momentum, with eight silicon implementations from Berkeley so far and external projects underway in India, the UK, and the US. Thanks in part to the open-source Chisel hardware design system, one 64-bit RISC-V core is half the area, half the power, and faster than a 32-bit ARM core with a similar pipeline made in the identical process.
Although it's hard to set aside our biases, we believe that RISC-V is the best and safest choice for a free, open RISC ISA. To expand the community for this free, open ISA, we will offer workshops and create a non-profit foundation to validate implementations and to maintain and evolve RISC-V.
The case is clearer for a free, open ISA than for a free, open OS. The core ISA is small and should not change, given the longevity of the basic RISC ideas, whereas algorithmic innovations and new application demands force continual OS evolution. It is also an interface standard and so easier to maintain and evolve than an implementation.
While the likely first beachhead for RISC-V is the IoT, our ambitious goal is grander: Just as Linux has become the standard OS for most computing devices, we envision RISC-V becoming the standard ISA for all computing devices.
— Krste Asanović is Professor and Director of the ASPIRE Lab at UC Berkeley. David Patterson is the Pardee Professor of Computer Science at UC Berkeley, and leader of the first RISC microprocessor. This blog is an abbreviated version of a whitepaper with the same title.