Fan-out wafer level packages are on the rise as vendors explore panel-based processes to make them less expensive.
Over the next year, volumes for fan-out wafer level packages (FO-WLPs) will be driven by application processors, RF transceivers and switches, power management integrated circuits, audio codec, connectivity modules, and radar modules for cars.
Many companies like the small form-factor, low-profile features of WLPs. But as they move to the next semiconductor nodes, the face of the die is too small to route all the I/O without using tiny solder balls that might have board reliability issues. This is especially true for audio codec and RF ICs.
In application processors, demands for thinner packages have focused on options such as the continued use of flip chip with a laminate substrate or embedded die. 3D ICs with TSVs to connect memory and logic have been ruled out due to supply chain, cost and thermal issues. Engineers have found no way to stop processor hot spots from pushing memory beyond its operating temperatures.
FO-WLP for application processors is a gamer changer compared with traditional flip chip on laminate substrates found in package-on-package (PoP) because a substrate is no longer required. That impacts substrate shipments in both unit volumes and revenue because the substrates used for the logic die in the bottom PoP have higher average selling prices.
With FO-WLP, as with any package, there is a demand for cost reduction. Several companies are researching, developing, or installing panel-based production lines, though many technical and economic issues still need to be considered.
The question is not whether the panel lines can be established, but what the right size of a large area panel is and whether the return on investment will be adequate. The analysis must include economic considerations that include calculations of part size and monthly panel loading, as well as yield and other factors.
With the constant pressure to decrease cost, companies are exploring a number of options for FO-WLPs. Deca has proposed a panel processing approach based on technology used in making solar panels. ASE recently invested $60 million to establish a production line in Taiwan for Deca’s processes. ASE also assembles a flip chip bumped die on a laminate panel that is marketed as a panel FO-WLP because the panel is considered large in area.
Unimicron is developing a panel version based on a glass line. Powertech Technology is also developing a panel process. In Korea, Samsung Electro-Mechanical and Samsung have teamed up to develop panel process for FO-WLP, but have not revealed details of its process. Nepes, also located in Korea, has a research program to investigate panel processing using an LCD production line. STATS ChipPAC has a large area panel FO-WLP development program in Singapore.
There are a number of technical issues to consider with panel production, including panel warpage during processing, material selection and coating methods, lithography tools, and singulation and testing of parts. Several consortia have been announced to allow companies to work together to tackle some of these issues. ASM Pacific, IME in Singapore, and Fraunhofer IZM in Berlin have proposed separate consortia.
The Fraunhofer consortium just held its kick-off meeting. Its consortium will work with end users to define future demand, with equipment and material suppliers to develop a process and provide standardization, and with OSATs to work on process integration. Fraunhofer will leverage its experience in embedded die to develop the process. Equipment is already in place and a number of companies have signed up.
There is high risk in spending scarce investment capital on the development of panel FO-WLP. Sharing the risk by participating in consortia may make it easier to investigate the viability of panel production.
-- E. Jan Vardaman is president of TechSearch International.