Last night, AMD demonstrated an eight-core, dual threaded 3 GHz desktop chip using its new Zen core narrowly edging out a similar high-end desktop CPU from archrival Intel.
The most impressive demo I saw on this week when the 2016 Intel Developer Forum is wrapping up came from Intel’s competitor Advanced Micro Devices at an event Wednesday night. AMD showed desktop and server versions of chips using its newly developed Zen CPU core, and to say the results were impressive would be an understatement.
Despite Intel demos of its next-generation Kaby Lake PC processor the surprise star of this week is Zen. AMD’s Summit Ridge desktop processor and its Naples server processor are the first two instantiations of AMD’s re-booted x86 core and processor architecture. AMD impressed attendees here in a manner we haven’t seen from the company in a decade by achieving a stated goal of delivering a 40% improvement in instruction level parallelism compared to its previous Excavator x86 core.
AMD lost the CPU performance lead in the late 2000’s through a series of design and delivery missteps on its Barcelona quad-core processor architecture. For much of the last decade AMD has tried to patch and tweak Barcelona to eke out more performance, but ultimately that design could not be fixed sufficiently to keep pace with Intel’s Core architecture. As a result, AMD’s market share has suffered in servers and high performance PCs.
AMD has been working on the Zen core since 2012. The CPU core is a completely new design that that will target Intel’s Core processor at every performance level. The first Zen chip was demonstrated earlier this year at Computex in Taiwan. On Wednesday night, AMD rolled out a more complete demonstration of the performance with a head-to-head comparison against Intel’s Core i7 Extreme Edition — an 8-core monster that sells for a suggested retail price of $1,100.
To achieve its performance goals, Zen provides a wider issue CPU core with improved branch predictors, simultaneous multithreading and lower latency caches. Specifically, Zen sports an 8MByte integrated 16-way shared L3, a 512KByte unified 8-way L2, and 64KByte low latency separate data and instruction L1 caches.
Together the redesigned memory subsystem delivers a 5x improvement in cache bandwidth. That contributes to what AMD said overall is a core with a 75% higher capacity to schedule instructions and a 50% greater ability to execute and issue them.
Mark Papermaster, AMD’s chief technologist, flashed a handful of slides providing a surprise overview of the Zen microarchitecture. Mike Clark, a lead architect on Zen, will give a deep dive on the design at next week’s Hot Chips event.
Next page: Zen edges out eight-core, 3 GHz Broadwell E