Is there a place for a volatile DRAM replacement? While the VLT as a DRAM replacement might be attractive, any success hinges on effective and innovative solutions to some major problems.
The use of latched threshold switching devices to replace a DRAM, where the off and latched states are used as the two memory logic states, is a recent proposal. With the apparent advantages of no requirement for a new technology, for a dynamic refresh cycle or a separate capacitor.
Two types of device offer this latched memory DRAM replacement possibility. One is based on a single crystal thyristor structure of the type proposed by Kilopass using their vertical layer thyristor structure VLT-RAM, illustrated in Figure 1, for which they have reported at MemCon 2016 significant progress.1 The second latching memory possibility could be achieved by the use of an amorphous film threshold switch, the latter offering the intriguing possibility of a high-density thin film 3D stacked structure.
Figure 1: Structure of VLT-RAM (Kilopass).
However, digging deeper into the claim of the absence of a capacitor, I find that like conventional DRAM — although not initially apparent — the thyristor memory of the Kilopass thyristor array structure illustrated in Figure 1 does rely on a capacitor to retain its data state under some operating conditions. The good news is it is an integral part of the device structure and is self refreshing.
The need for a capacitor arises from the conflict related to the need to simultaneously maintain the latching current for some devices in a memory array while reducing the voltage or current to zero on other devices in the array in order to unlatch them. This problem can only be solved by the use of a capacitor to momentarily provide a holding current for all devices in the conducting state along bit and word lines to ensure no loss of data, while at the same time switching some devices between logic states.
For a thin-film chalcogenide threshold switch equivalent, the thermal capacitance and structural relaxation will provide the data-retention possibility — more on that later in this column. While the VLT as a DRAM replacement might be attractive, any future success will hinge on effective and innovative solutions to these problems.
Before exploring in a little more detail how these problems arise and the means by which Kilopass have solved them I asked Bruce Bateman, senior principal engineer at Kilopass, for confirmation of the need for a capacitor. In his recent presentation at Memcon 2016 he acknowledged the ability of the Kilopass VLT-RAM structure to go outside of its DC operating window for periods from 10 to 100ns without loss of data. I asked him for some clarification on this aspect of the operation of the VLT-RAM.
“The retention time of the cell when biased outside the DC operating window is due to the self capacitance of the structure- i.e. the junction capacitance of the diodes in the PNPN stack.”
Meaning, the self capacitance is able to supply sufficient current to maintain the data state if the device is momentarily taken outside its normal operating range and subjected to zero or reverse voltage. This means any successful write scheme must be able to take the selected device outside its operating window for sufficient time to fully discharge any self capacitance and to allow any long lifetime carriers to be absorbed. While at the same time ensuring any excursions below the holding current and voltage for unselected devices in the conducting state are of a short enough duration to allow the device to recover to that state.
Latching memory problems 101
Figure 2: Example of latching memory problems.
Figure 2 (a) illustrates a section of a latching array with the generic symbol for a latching memory device with rectification properties (The solid circle representing a device in its latched or conducting state). The voltage Vm is required for maintaining any latched devices in the conducting state.
Consider the simple case. Figure 2(b) of a rectifying latch without any associated capacitance and a section of the array with the selected device, circled in red, and all nearest neighbors in the conducting or latched state.
Any attempt to reduce the voltage across the selected device to zero volts or a reverse voltage by applying a positive voltage greater than Vm to the cathode will successfully unlatch the selected device, however it will also unlatch the nearest neighbor on the word line, i.e. the device below it in figure 2(b). Similarly applying a negative pulse to the bit line will again unlatch the selected device as well as its nearest neighbors on the bit line.
The same unwanted problem of switching of nearest neighbors occurs when attempting to write a device from the unlatched state to the latched state. These are illustrated in Figure 2(c).
Attempts at using half selection pulses on word and bit lines suffer similar problems, in some cases if devices are in the latched state large unwanted currents will flow in unselected devices as illustrated in Figure 2(d). I will leave readers to explore other possibilities.
Those skilled in the art might see a solution by momentarily raising the voltage on all unselected word or bit lines, although that is a step in the right direction without a capacitor it does not provide a solution.
Figure 3 is a simple summary of what is necessary to deal with the problem when latching memory devices are subjected to zero volts or reverse voltages. When writing a selected device to its non-conducting state, the voltage across the bit and word lines is reduced to zero. The capacitor associated with the selected device must be fully discharged state while maintaining sufficient keep alive current for those unselected latched devices, which also get subjected to zero volts or negative voltages outside the normal operating range.
Figure 3. The role of the retention capacitor.
Kilopass's VLT solution
Figure 4 is one example, of the Kilopass innovative solution for writing from the off-to- on state for their VLT memory array, the red circled device, others can be found in Bateman's presentation.2
Figure 4. The VLT-RAM solution.
In the normal standby state, a voltage VDDA is applied to the bit lines with the current through the VLTs controlled by a single constant current sink shared by all word lines. Because the constant current is shared by all devices, the current through the conducting devices will vary as the ratio of the number of devices in the on and off states. This scheme maintains the word lines at a voltage of V(WL_SB) with the standby voltage across each device of (VDDA -V(WL_SB)).
When writing the selected device from the off-to-on state the voltage on all non selected bit lines is reduced from VDDA to a value VNSEL. At the same time the highlighted transistor on the word line reduces the word line voltage to a value V(WL_W0). The combined voltage across the selected device then exceeds the threshold value and the device switches to its conducting state, discharging the bit line associated with the selected device.
The device of particular interest in Figure 4 is circled in green which illustrates both the problem and the solution. When the combined effect of the voltages of the non-select pulse and word line voltages goes to zero it is the internal capacitance which provides enough current to maintain this unselected device latched until with the write operation complete the voltage VDDA reappears on the bit line.
A similar scheme is used for writing a selected device from the on-to-off state.
While most of the demonstration of VLT has been at the 55nm node, Kilopass predict they will be able to scale the VLT to 10nm. In that respect I asked Bateman if the variation of retention time, (over a range of from 10 to 100nsecs), is related to the size of the structure or the difference between a discrete device and a device in an memory array structure? His view was:
“I would say neither. The size of the structure (in terms of the surface layout area of the vertical thyristor) cancels itself out in terms of the ON/OFF stability. The ON/OFF current of the cell scales as the horizontal area of the thyristor stack. But so does the junction capacitance of the internal nodes. The rate at which the current changes the internal voltages stays the same as the lateral dimensions of the thyristor stack are changed.“