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IEEE S3S 2017 Showcases Monolithic 3D Technologies

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alex_m1
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Re: one advantage of 3D
alex_m1   10/14/2017 3:16:14 PM
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Thanks realjjj.

realjjj
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Re: one advantage of 3D
realjjj   10/11/2017 11:36:11 PM
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The idea is to have process steps that address multiple layers at once as opposed to repeating every step with every layer. Some basic info, you can search for more if you need to:

https://www.youtube.com/watch?v=ANHzVOiUwGI

http://www.chipworks.com/about-chipworks/overview/blog/intelmicron-detail-their-3d-nand-iedm

With logic it would be a lot more difficult but the concept is appealing to enable solid cost scaling on the vertical.

alex_m1
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Re: one advantage of 3D
alex_m1   10/11/2017 1:43:16 PM
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>>  Plus, if new approaches can be devised, which reduce or even eliminate the extra cost of adding an extra layer (following for instance 3D NAND approaches)  Interesting. What are those 3D NAND approaches?

Or_Bach
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Re: "1,000x total system benefit"?
Or_Bach   10/10/2017 10:26:51 PM
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Demonstrating on >50x vs. 7nm SoC, with real device, integrated in US, is exectly the objective of the 3DSoC program.

DumbCook
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"1,000x total system benefit"?
DumbCook   10/6/2017 9:50:40 PM
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"...We will also describe how such an integration technology could be used to improve performance, reduce power and cost of most computer systems, suggestive of a 1,000x total system benefit."  1,000x would be equivalent to 10 generations of classic CMOS scaling (assuming 2x improvement at each generation).  It will be great if 100x, or even 10x, performance gain can be actually demonstrated on actual hardware.

bruce.b.doris
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Re: Perfect timing
bruce.b.doris   10/4/2017 1:37:38 AM
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Challenges of CMOS scaling beyond 7nm node are daunting. Now more than ever novel packaging is needed to bring different components together. The need for more sophisticated mobile devices that can run for ever with our re charging is not satisfied. However the promose of new ultra low power options seems just on the horizon. Also now that FDSOI is available in foundries means that volume sales will enable this technology to be available for all applications.  It will be great to learn more about the advances in 3DI, SOI and Sub Vt all in one venue at the IEEE 2017 S3S Conferenc in SF on Oct 16. Tutorials on 3DI and FDSOI this year make a compelling case to attend the week long event or just come for a day to learn about one of your favorite topics. I am personally planing to attend the entire conference as well as the FDSOI workshop on thursday.  

Or_Bach
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Re: More than just 3D
Or_Bach   10/3/2017 9:58:13 AM
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And having, the MICROSYSTEMS TECHNOLOGY OFFICE DIRECTOR, Dr. William Chappell and the PROGRAM MANAGER, Dr. Linton Salmon attending the conference, provides direct access to learn more about this Beyond Scaling: An Electronics Resurgence Initiative ("ERI").

savitale
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More than just 3D
savitale   10/3/2017 9:36:11 AM
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The ERI, also known as PAGE 3 (after the 3rd page of Gordon Moore's famous paper) is broader than just 3D. It includes new circuit topologies and architectures as well. There is also mention of new materials and devices but I'm not sure how serious DARPA is about that. 3D is definitely an important component as it is the most straightforward way to bring memory closer to logic, both phyiscally and electrically. The are other ways to do compute-in-memory or memory-in-compute as well. All of these topics are spot-on for the IEEE S3S Conference, and I expect that there will valuable disussions about this new DARPA initiative.

Or_Bach
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Re: one advantage of 3D
Or_Bach   10/3/2017 3:40:55 AM
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DARPA is looking for monolithic 3D to provide more than 50x better SoC compare to 2D 7nm at comparable cost. Such improvement is far beyond what could be achieved with 2D scaling!!! Come to the IEEE S3S 2017 conference to learn more about this.

realjjj
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Re: one advantage of 3D
realjjj   10/2/2017 9:42:48 PM
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Wasn't arguing that stacking 2D layers doesn't improve costs, just that an approach more like 3D NAND would offer better scaling. CoolCube is great because it might enable 3D soon and pave the way for more advanced solutions, make the transition a bit easier.

In theory we should compare 3D vs 3D not vs 2D, the horizontal remains relevant.

In phones a 5W SoC might work but with glasses maybe we need a 200mW SoC , including memory and every inch of perf will matter for a better GPU or a better "awareness processor"(sensor hub and AI). This kind of efficiency, perf and cost would also enable all kinds of robots. AI fits 3D well too so that's another plus as you can never have enough intelligence. So traditional 2D for the most advanced nodes would be phased out but there would be a huge market for advanced 3D. The shift away from discrete memory would be great for foundries and customers but a negative for some.

Not sure about 3D for older nodes, with 2D layers (CoolCube) maybe it would work but with "true 3D" (like NAND), the development costs might be too high for the lower ASP products that tend to use such nodes.  

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