Commercial tools can help to address congestion areas; however, it is important to first understand what is causing the congestion problems.
Over the last decade the size and complexity of FPGA designs have continued to grow for many market applications, mainly due to the additional functionality and increased performance and size of FPGA devices. Considering this, FPGA designers must take into account the multiple IP sources, code reuse, and the associated design constraints for synthesis and forward annotated vendor specific place and route constraints.
FPGA designers are continuously being pushed to accelerate schedules and reduce their development costs giving rise to more licensed IP cores in designs and more in-house design code reuse. It is critical that the synthesis tools can handle various sources of IP, including their constraints (see Figure 1).
Figure 1 - Versatile synthesis flow for RTL, IP and Constraint handling
Once a project is setup, designers need to create their initial design constraints and import IP specific constraints. There are several types of constraints from timing to physical, as listed below.
o Declaring clocks
o Declaring clock groups
o Defining multicycle paths and false-paths
Physical constraints and attributes
o IO location constraints
o Attributes for functional safety
o Mapping control for memories, DSPs
By adding the full set of constraints to synthesis, the tool can forward annotate and place and route constraints directly.
It is important for FPGA designers to correctly define the constraints for primary clocks for I/O, black-boxes, and generated clock nets. A common mistake designers make is over constraining their design, which can put an extra burden on synthesis and directly impact achievable speed, area, and runtime for their design. Alternatively, better constraints can translate to a better input netlist for the vendor specific place and route tools, but can also cause additional runtime and congestion issues.
With the widely-expanding capabilities and capacities of FPGAs, implementing FPGAs is not always a push-button process. Commercial tools can help to address congestion areas; however, it is important to first understand what is causing the congestion problems.
Problems can arise from high resource utilization, aggressive timing constraints, placement, logic packing, and high interconnectivity among other causes. In many cases, more than one congestion reducing technique is needed to successfully route a challenging design. If using Synplify (the tool Synopsys makes), designers should check the log file for an early congestion estimate. The place and route logs provide critical warnings about sub-optimal placements (clock buffers, gated clocks, etc.), as well as information about estimated congestion in placer and any initial congestion in router.
FPGAs are attractive as a platform processing solution in product implementation due to their high processing bandwidth, scalability, and versatility for many applications. While the ability to integrate many sub-systems into a single FPGA is overall beneficial, it can be more challenging to apply the correct constraints and to get the design through from RTL to bitstream. A commercial tool, such as Synplify, can enable designers to define the initial constraints, tune them for the design, and help identify bottlenecks that may cause congestion issues in the flow.
—Joe Mallett is a senior product marketing manager for FPGA-based synthesis software tools at Synopsys. He has 20 years of experience in design and implementation within the semiconductor and EDA industries. Before joining Synopsys, Joe was a senior product marketing manager at Xilinx Semiconductor where he worked to define and launch FPGA products. His background includes SoC design/prototyping, embedded software, HDL synthesis, IP, and product/segment marketing. He holds a BSEE from Portland State University.