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Here are some of the important facts on differences of Bulk Si,
FDSOI and FinFETs.
Bulk Si successfully ran several technology nodes such as 95,
65, 45, 35 but ends at 28nm. In order to suppress transistor
leakage current or drain/source punchthrough a combination
of channel doping and retrograde channel implant just below
the Si surface were used for Bulk Si. However, such a
combination of the channel doping and retrograde implant
has a limit as the channel or gate length, Lg decreases to
20nm because precise control of shallower retrograde channel
implant just below the Si surface becomes increasingly more
difficult, complex and not so effective any more in
manufacturing, resulting in high device variabilities or
instabilities in transistor electrical transfer characteristics due
to high transistor leakage current due to poor process control
and manufacturability. That is why Intel adopted 22nm
FDSOI is not the cost issue but transistor device physics
issue. FDSOI has two most critical issues: its scalerbility and
manufacturability. IBM invented FDSOI technology over a
decade ago and created International SOI consortium to
develop and manufacture FDSOI but not manufacturable
today at any technology node yet. IBM exited FDSOI a long
FDSOI has such a very simple structure consisted of high K
metal gate, thin SOI and thick oxide substrate that often
make unware of the real issues with FDSOI. The 28nm
Bulk is in mass production for several years by major
semiconductor companies such as Intel, TSMC, Samsung
and others but 28nm FDSOI is not manufacturable today.
Even if manufactured today, it would not be
competitive with 28nm Bulk because SOI wafe rcost is
very much higher than bulk Si wafer.
FDSOI is not scaleable. The beauty of FinFETS over FDSOI
is its scaleability. The thin SOI is the key component of
FDSOI to suppress transistor leakage current or short
channel effects. In order to suppress transistor leakage
current for 20nm FDSOI a 5nm thin SOI is required while
for 20nm FinFETs the Finwidth at the bottom of Fin that is
equivalent to SOI thickness for FDSOI requires 20nm.
What a large difference! 20nm for FinFETs vs 5nm for
FDSOI for suppressing transistor leakage current or short
channel effects. That is why Intel's FinFETs are scaleable
to the end of the roadmap, but not FDSOI, not even 14nm
FDSOI that requires 3.5nm SOI that is close to the
ultimate quantum confinement limit(3nm). That is why
Intel 14nm FinFETs will be high volume manufactured in
2015 at the same time when TSMC 16nm FinFETs volume
manufacturing starts. Major Semiconductor companies
will adopt the FinFETs, not FDSOI.
The 3.5nm SOI thickness for14nm FDSOI is estimated from
simulation data published by Professor J. G. Fossum,
university of Florida in his book "Fundamentals of Ultra-thin
body MOSFETs and FinFETs". See Fig. 3.8 on FD/SOI
MOSFET with thick BOX.
In my opinion even with 6nm SOI thickness for 14nm
FDSOI the 6nm SOI is too thin to incorporate SIGe for PFET
in order to be effective. FinFET dose not require a strain
knob for PFET as well as NFET. Fin-Width has a trepizoidal
shape that means the Fin-Width decreases with Fin-Hight.
As a result, most of the high I-on current comes from the
upper narrow portion of the Fin because the narrow region
is fully inverted just like double gate transistor. For double
gate transistor the hightest transistor on-current occurs
when both top and bottom transistors become inverted.
According to just published 2014 VLSI abstracts the 14nm
FDSOI with forward back bias(FBB) is not manufacturable
yet, just demonstration. I doubt it is manufactured.
I repeat FDSOI has not been volume manufactured at any
technology yet, and will not be. Major semiconductor
companies will adopt FinFETs, not FDSOI.
You disagree that 14nm technology means a 14nm gate or
channel length for 14nm FinFFETs. You said that is not true,
known across all companies. "The technology node number
is just a label.......... ." I can't disagree more. When Intel
and TSMC announced 14nm and 16nm FinFETs respectively
for high volume manufacturing in 2015, they meant 14nm
and 16nm channel or gate length, Lg. 2014 VLSI symposium
featuring a 10nm FinFET platform means a 10nm channel or
gate length, Lg. Otherwise, we can't talk about transistor
leakage current or short channel effects that are the
determining factors for FinFET scailerbility.
You miss quoted me here. I didn't say "only the top of the
channel....." I said most of the high I-on current comes from
the upper narrow portion of FinW(width) because the narrow
region is fully inverted....etc." An important thing to
remember here is that not the entire FinW area is inverted.
Because of a trapezoidal nature of Fin shape, FinW at the
bottom is much wider. Therefore, the FinW at bottom is not
inverted, instead depleted. That is why the high I-on current
comes from the upper narrow inverted FinW region. FinFET
doesn't require an additional strain knob that may impact
adversely the un-doped inverted Fin region. That is why
Intel's 22nm and 14nm FinFETs in volume manufactured
today don't use additional strain. The maximum high I-on
current for Intel 14nm FinFET is achieved by maximizing
the un-doped upper fully inverted FinW region and
minimizing the fully depleted FinW region at bottom.