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ASML selling more multipatterning tools than EUV
resistion   6/26/2014 9:57:48 AM
The last earnings meeting they were saying 24 NXT-1970 multipatterning tools in Q1 alone, while hoping to squeak out a few more NXE:3300 EUV this year. Two things boggle me: 1) why continue with EUV if multipatterning is already a good business for ASML, and customers are paying (including the same as paying for EUV)? and 2) why continue the traditional Moore's Law shrink if the traditional cost reduction model is not viable anymore (due to new lithographies, high-k, fins, future channels, etc.)?

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Your opinion request...this may be the answer?
techgc   5/3/2014 2:14:49 PM
Monolythic GaAS combining optics and electonics on one die.  In development for 30 years and now moving from R+D to commercialization by DR. Talyor (U.Conn Tech Dean, PHD) at POET Technologies.   

Many X clockspeed performance of Si (I am not exaggerating) , up to 70% less power of current SI models.  Can be built with existing Semi fab equipement.   Little known company that is "coming out to the wolrd" exploding with 400% stock performance this year.   

This post may come off as a pump mail (full discolure, I am a shareholder), this said - I highly encourage you to check this out - if only for your interest.    

BAE verified technology. NASA funded (previously), design kits are now turning into a fabless licensing play (see ARM), with first partner being announced within months.

Intersted in any feedback you have.  



David Ashton
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Re: Intel Cost Slides
David Ashton   4/3/2014 8:32:47 PM
@AHK0....  point taken....but using two variables in your yardstick does complicate matters a bit?

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Re: Intel Cost Slides
AKH0   4/3/2014 8:26:31 PM
Moore's original paper says "the number of components per integrated circuit with minimum cost". The Wikipedia article seem to forget the minimum cost.

David Ashton
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Re: Intel Cost Slides
David Ashton   4/3/2014 5:59:47 PM

"1) Moore's law is about cost, not about gate length, nor performance, nor leakage"


"Moore's law is the observation that, over the history of computing hardware, the number of transistors on integrated circuits doubles approximately every two years. The law is named after Intel co-founder Gordon E. Moore, who described the trend in his 1965 paper."

I think performance would be a better yardstick, but we have to stick to number of transistors.  3D ICs will keep it going a bit longer, maybe.

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Re: Intel Cost Slides
AKH0   4/3/2014 5:11:29 PM
Dear Sang Kim,

I'd apprciate if you would read my previous comments.

1) Moore's law is a bout cost, not about gate length, nor performance, nor leakage. Those are historically governed by Dennard's scaling and we can argue whether it still holds or not. But the discussion here is about the cost. As I pointed out earlier, Moore's law was made in the bipolar days. It was extended through NMOS and later CMOS days because they integrated chips continued to made at a lower cost per component.

2) ST demonstrated U8540 chips two years ago and it was shown to drop total power by 35% copared to 28nm bulk. Ironically ST-Ericson was disintegrated shortly after. So there is no product in the market. ST had continued making test chips for a handful of customers and all those that I am aware of had seen the benefit. However, ST does not have the fab capicity and said they are announcing the fab partner soon. So there is not such thing as ST "is not able to manufacture". There is a bog difference between "not being able to" and "not doing".

3) I have not seen any data suggesting 20nm bulk had leakage issue. Several companies in fact made the announcement that they will design in 20nm as their next node after 28nm. Others complained that there is not enough performance gain and would like to go directly to FinFET.

4) When talking about the FinFET performance what is the reference points? As for the leakage, their SoC paper used devices at 108nm pitch to show ULP leakage -- as opposed to 90nm pitch for other devices, which means these are roughly at Lg = 30+18nm = 48nm! I am confident you can get the same level of the leakage in a bulk planar device with the same gate length. As for the performance, both Intel and TSMC published data normalized to the footprint and not the actual device width. This is actually how TSMC claims performance better than Intel. While we can argue if this is thr right choice or not, first of all none of them were transparent in reporting numbers. Second, the higher current comes at the expense of higher capacitance, so it is not clear if there is net AC performance. Intel showed a RO delay of 13ps at VLSI'12 at 0.7V. That device would be about 10ps at 1V. Their 45nm node at the same leakage was 5ps! TSMC even did not show this. They showed a TCAD simulation of aggragate of what they claim to be representative of circuit performance.

5) It's been a while that node number has nothing to do with gate length. All discussions predicting requirements of Lg vs thickness are irrelevant here. BTW, quantum confinemnet is nothing to be scared of. It's already in play even in buld devices (you have a triangular quantum well vs the square shaped in FinFET). The inversion layer thickness is only 2-3nm in any advanced device. That's all you need to make a transitor. Yes, variability is a problem but it kicks in  at much thicker films, and unfortunately FinFET does not have any magic to offer.

6) Please read TSMC's paper again. Minimum gate length is 30nm -- and so is in Intel's although they decided to call it 26nm at a later point. Their low leakage device is also at 50nm gate length. As I mentioned above, technology node has nothing to do with gate length.

7) As I mentioned in my previous comment, IBM developed FDSOI along with its partners and transferred it to partner sites. There is no skipping here. This is very much same as the 28nm LP devices that powers iphones today. It was develped as a part of common platform and transferred to parners sites. BTW, ST has a paper in the upcoming VLSI. Channel length is not 14nm and channel thcikness is 6nm. It has the same gate pitch and metal pitch of what the FinFET camp calls 14nm.

8) I invted you to attend the conference in October in the bay area and you can see if there is harmoney or not. I beleive the organizing commettees of the three conferenced agreeded there is enough overlap to merge those together. But you are welcome to attend and comment if you think otherwise.

Thank you!


Susan Rambo
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Keynoter approved
Susan Rambo   4/2/2014 7:22:45 PM
Bunnie Huang, in his keynote today, quoted from this article and said it was a really interesting read. That's why it's back on the EE Times home page. Great keynote today. Now that Moore's Law is slowing down, it's better for smaller companies that want to spend more time on hardware and software design and optimization rather than having to plan for the next few months when Moore's Law was going to make their product obsolete. He said Moore's Law favored bigger companies that could have several teams working on next generation simultaneously.

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Re: Intel Cost Slides
michgan0   3/31/2014 1:23:18 AM

Sang Kim


Thanks for your comments.


Two key issues with FD-SOI are its manufacturability and  

scalerbility as I pointed out. 


1) I said Moore's law ends at 28nm bulk Si. Moore in 1965

 couldn't predict a new FinFETs era beyond the 28nm bulk Si,

 and most of all, the new FinFETs can be extended to the end

 of the roadmap. 


2) Regardless the total fabrication costs, ST is not able to

 manufacture 28nm FDSOI even today. Even if 28nm FDSOI

 were manufactured today, it would not be competitive with 

 the bulk Si 28nm as I described.


3) Bulk Si technology stoped at 28nm! Samsung and TSMC

 indeed fabricated the planar bulk at 20nm, but the 20nm

 planar bulk transistor leakage current was very high due 

 to the short channel effects. The 20nm planar bulk was

 abandoned. TSMC adopted to manufacture 16nm FinFETs. 


4) The first FinFETs are introduced by Intel at 22nm node,

 and is in mass production over two years. Since at transistor

 level FinFETs show the lowest leakage current and highest

 performance. I expect the same at the product level. There

 are no rivals. 


5) Absolutely there is a physical limit. I said that 5nm node

 is considered to be practical end of the roadmap. The next

 3nm FinFETs will require a maximum 3nm channel thickness

 in order to suppress the transistor leakage current. At the

 3nm channel thickness, however,a new quantum mechanical

 phenomenon called quantum confinement occurs, resulting in

 an increase in Vt and large statistical variabilities in transistor

 transfer characteristics. This is because in the quantum

 confinement region the channel electrons don't behave like

 electron particles any more, instead, behaving like electron

 waves. As a result, the electron particle based classical

 Maxwell- Boltzmann statistics is no longer applicable, instead

 subject to Heisenberg uncertainty.


6) TSMC's 16nm node does really mean 16nm channel length

 or gate length, Lg. Intel and TSMC FinFETs do not require a

 gate length of 30nm or 50nm to obtain very low transistor

 leakage current. In order to suppress transistor leakage current

 or short channel effects for 16nm FinFETs the Fin-width at the

 bottom of transistor has to be only equal to or smaller than the

 channel length or gate length. That is, 16nm or smaller

 Fin-width is only required to suppress the transistor leakage

 current. The Fin-width of FinFETs is equivalent to the channel

 thickness of FDSOI. 16nm FDSOI for comparison 4nm

 channel thickness is required to suppress transistor leakage

 current. What a large difference! 16nm channel thickness

 for 16nm FinFETs vs 4nm channel thickness for 16nm FDSOI.


7) Promoting FDSOI is the major aspect of SOI Consortium.


8) IBM FDSOI skipped 28nm, 22nm, and will skip also 16nm

 and 14nm nodes. At what technology node IBM FD-SOI 

 will be manufactured? At 10nm node? IBM exited FDSOI long

 ago.I doubt that 14nm FDSOI will be manufacturable by ST

 because 14nm FDSOI requires SOI thickness of 3.5nm that

 is very close to the quantum confinement limit(3nm) as I

 described above. 


9) I don't understand why IEEE decided to merge SOI, Sub-Vt and 3D, and create a new S3S IEEE conference. I don't see

 such a strong harmony between these topics. Why these topics

 can't be presented in the well known and reputable, already

 existing IEEE conferences such as IEDM, VLSI and others?

 It seems too early to talk about creating IEEE conference for

 S3S. Who will be attracted by SOI, sub-Vt and and 3D at this

 14nm FinFETs era?    

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Re: Intel Cost Slides
AKH0   3/26/2014 1:03:46 AM
Dear Sang Kim, I am afraid you are mixing too many items here.

1) Moore's law was based on the observation made on bipolar IC's. By your argument, it was fulfilled the day CMOS was born.

2) Cost of the bare Si wafer is just a fraction of the total fabrication cost. A cost difference of about $400 between Si and SOI wafers is well absorbed by reduction in the number of masks. I'll asure you, STM is one of the most cost-sensitive companies and would not do FDSOI if it would cost more. On the other hand, Intel is known for large margines. So, when Mr. Bohr claims bulk FinFET adds only 2% to process cost, I put a big question mark there.

3) Bulk Si technology did not stop at 28nm. There is bulk planar technologies by both Samsung and TSMC at 20nm. IMO, fabless companies where better off going to 20nm than getting distracted by the lure of FinFET, just to waste more than a year of design and finally figuring out things are not as rosy as the powerpoints show.

4) Contrary to all claims, I do not see big advantage at product level by FinFET products that are out there. The original claim was FinFET allows reduction in operating voltage of 200mV at the same performance, a 40% drop in active power just from FinFET (let alone natural ~30% reduction in power from node to node). This was never seen in products.

5) There is absolutely nothing in semiconductor physics that says 5nm is the minimum channel thickness.

6) Technology node is note represented by gate length. A 14nm node does not mean 14nm gate length. For all I see from publications, Intel and TSMC FinFET are using a gate length of 30nm or longer (up to 50nm for very low leakage devices), while FDSOI is at 25nm or smaller.

7) IBM is a member of the SOI Industry Consortium:

Promoting FDSOI is only one aspect of the consortium. SOI market spans far more, including RF, MEMS, etc.

8) IBM did not exit FDSOI. What will be 14nm FDSOI offering by ST was a joint development that started at IBM facility and was transfered to ST's site. This is very similar to other joint developments IBM had done with ISDA partners in the past (including the 28nm bulk planar that powers iphones). The fact that IBM decided to use SOI FinFET for its own server products is also very similar to IBM's use of PDSOI at 45nm, 32nm, and 22nm, despite the fact that IBM developed both bulk and PDSOI technolgies at each node.

9) S3S is an IEEE conference. IEEE decided to merge SOI conference, sub-Vt confernce, and 3D, because the committee beleived there is a strong harmony between these topics, despite covering seemingly different fields.



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Re: Intel Cost Slides
michgan0   3/25/2014 11:41:39 PM

Sang Kim


Moore's Law predicted in 1965 was fulfilled because 

Moore's prediction in my opinion was based on the bulk 

silicon technology that ends at 28nm and not beyond, 

definitely not 7nm.


ST claims the FDSOI technology will continue Moore's law. 

However, look at some of the facts on FD-SOI. The 28nm

bulk silicon is in mass production over several years by 

major semiconductor companies such as Intel, TSMC, 

Samsung and others. 12 inch bulk silicon wafers currently 

are used in mass production today in order to maximize 

28nm transistor yields and minimize transistor process costs

at the same time. Therefore, even if 28nm FD-SOI were 

manufactured today, it would not be competitive with 28nm 

bulk silicon because 12 inch SOI wafer costs more than 

2 x 12 inch bulk silicon wafer. 


Here are some other facts. The bulk silicon technology ends 

at 28nm node because of the excessive transistor leakage 

current or short channel effects. That is why new FinTETs

are introduced by Intel at 20/22nm nodes. Intel is the only 

one today in mass production of 22nm bulk FinFETs over 

two years. TSMC 16nm bulk FinFETs will be volume 

manufactured possibly in 2015. The beauty of FinFETs over 

FD-SOI is its scalability. According to transistor device 

physics the transistor channel thickness of 5nm is 

considered to be the practical end of the roadmap. For 14nm 

FD-SOI the SOI thickness of 3.5nm is required to suppress 

transistor leakage current. It means that the 3.5nm is not 

manufacturable. For 14nm FinFETs, on the other hand, the 

Fin width that is equivalent to SOI thickness will require 

14nm. That is why FinFETs can be extended to the end of 

the roadmap, but FD-SOI can not be extended even to 

14nm FD-SOI.


IBM invented FD-SOI and ET(extremely thin) SOI, and

created International SOI Consortium in order to develop 

and manufacture them, but couldn't manufacture them

at any technology node yet. IBM exited FD-SOI and 

ET-SOI long ago! That is why I seriously doubt that the 

heavily SOI based S3S can compete with Intel's 22nm 

FinFETs. At what technology node can the S3S technology 

demonstrate its manufactrability, 28nm? 


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