The success of NAND flash memory in the semiconductor market is mainly driven by continuous and tremendous growth in the mobile phone and tablet PC markets, and the growth of adoption of high performance solid state drives (SSDs) as a replacement for hard drives in computers. As Intel and Micron jointly announced last year, a NAND flash product with a terabit capacity, comprising a simple stack of several dice, can be realized with the advent of 20-nm manufacturing technology in conjunction with a break-through concept in cell architecture.
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During the past years, NAND flash has enjoyed the highest density among the commercial memories due to its excellent physical scalability and multi-level cell (MLC) approach with two or three bits per cell. However, the recent demand spike for NAND flash memories in portable electronics has resulted in a much drastic scaling down of the device structure of NAND to obtain higher density, faster speed and lower bit cost devices. The aggressive scaling of a cell size in NAND flash memory is expected to face severe barriers in sub-20-nm floating gate-based flash cell with conventional architecture.
In response to the challenges mentioned, Intel and Micron’s joint venture for process development, IM Flash Technologies (IMFT), aggressively pursued a NAND cell shrink, and, as a result, has successfully developed and manufactured high density multi-level NAND flash memories with a 20-nm design rule for the first time. IMFT also revealed an innovative memory structure with the introduction of a fully planar floating gate cell design. IMFT, often considered a leader in the NAND flash manufacturing process, has introduced a cell planarization integrating with high-k/metal gate (HKMG) stack that would considerably overcome many of the physical and electrical scaling challenges brought on by moving to the 20-nm node or further beyond.
UBM TechInsights recently analyzed IMFT’s 20-nm 64Gbit MLC NAND to get a better understanding of the advanced process technologies and innovative cell architecture.
By introducing the 20-nm process technology in the production of their 64-Gbit MLCNAND flash memory, IMFT establishes itself as the leader in new process node implementation. Measuring in with a die size of just 117 mm2 , this NAND device features an area size that is approximately a 30 percent reduction over the IMFT’s existing 25-nm 64-Gbit NAND flash. IMFT’s 64-Gbit NAND flash is fabricated in a single poly, metal gate and triple metal levels and is distributed in a 48-pin lead-free TSOP package. The 64-Gbit of single flash memory die is divided into four banks with one-sided bond pad arrangement and memory area efficiency is 52% which is comparable to previous 25-nm 64-Gbit NAND device having the die size of 162 mm2 .
In a conventional NAND floating gate cell, the control gate (CG) and inter-poly dielectric wrap around the floating gate (FG) and coupling factor greatly relies on the floating gate sidewalls as shown in the figure below.
For the 20-nm and below technology node, the cell spacing is already too narrow to allow a control gate plug between the floating gates. As a result, the NAND flash memory will have to adopt a planar cell configuration by eliminating the control gate-floating gate wraparound. Â
Charge trapping-based flash (CTF) memory had been considered as an alternative, with CTF having a planar cell structure, but unfortunately we have yet to see a successful debut in NAND production quite yet. With all these factors at play, metal as control gate in combination with a stack of high-k inter-gate dielectrics (IGD) above thinner floating gate would be the potential solution to continue the scaling of NAND flash beyond the 20-nm node with existing floating gate-based NAND flash technology.
Key technologies in the process and new flash cell structure
IMFT's 20-nm technology with a fully planar cell structure and key process advances have overcome several critical problems of conventional floating gate cell architectures in such a small flash device:
•   Control gate (CG) poly-Si filling to narrower space between adjacent floating gates
•   Cell-to-cell interference
•   Scaling limitation of inter-poly dielectric (IPD) and smaller CG to FG coupling ratio. Â
In order to manufacture a 20-nm NAND cell, advanced cell pitch reduction techniques (such as double patterning technology) are used for critical lithographic steps. To pattern below the 20-nm design rule, quad patterning technology will also have to be implemented to overcome the limitation of 193 nm ArF immersion double patterning. This, however, could be still a ways away as the extreme ultraviolet lithography (EUV) tool required to address this patterning issue is still too expensive for flash memory production. For this NAND component, a single flash cell measures around 40-nm in both the wordline and the bitline direction yielding a physical cell area of 0.0017 µm2 . That makes this cell most likely the smallest cell in NAND production. A planar floating gate structure has been implemented in this NAND device, in conjunction with thin polysilicon floating gate, a stack of high-k inter-gate dielectrics (IGD), and metal control gate. Â
For a new cell structure, oxide-nitride-oxide (ONO) inter-gate dielectric layer is replaced by a stack of high-k dielectrics to restore the FG to CG coupling ratio which should be reduced in planar cell structure. Thinner polysilicon floating gate technology is likely adopted to lower the cell-to-cell interference. A metal gate-based wordline is defined by etching the multiple gate stacks using the hard mask layer. As the cell pitch is aggressively scaled, the increased capacitance coupling between cells is a severe issue, since increased cell-to-cell interference leads to cell performance degradation and reliability problem. In order to overcome these problems, an air gap isolation process is adopted for both cell gates and metal 1 bitlines. An air gap structure has been reported to act as a low dielectric constant gap filling materials. The bitline contacts are formed as a staggered layout to obtain better lithographic margin, and a NAND string has 68 wordlines.
New cell architecture combined with key integration technologies observed from IMFT’s 20-nm MLC NAND flash is very promising to further extend the life span of conventional floating gate flash memory with more aggressive cell scaling. However, with a further reduced geometry of floating gate, the electrons captured will be drastically decreased, which could result in the need to manage less than 20 electrons in 1x-nm MLC NAND flash. That’s why novel device concepts or alternative memory solutions, such as those found in IMFT’s latest NAND flash device, reveal a preparedness to replace NAND flash memory in near future since scaling demand and reliability challenges will be much higher in dominant mobile applications. For example, the CTF seen in this NAND coupled with 3-D configuration could be seen as a viable near-term alternative to current planar NAND flash technology while a large variety of new memory concepts are emerging and competing for the replacement of NAND flash memory. Floating gate NAND flash will eventually arrive at its scaling limit but it’s not quite hitting the wall just yet. It will be very interesting to see what changes IMFT, and other flash manufacturers, incorporate to overcome these scaling limitations in the future.
Young-Min Kwon is a senior process analyst at UBM TechInsights, a sister company to EE Times.
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