At a RISC-V workshop here, Esperanto will demonstrate RTL, presumably running in an FPGA, handling neural-networking jobs such as image recognition. The company’s general-purpose processors haven’t taped out yet but will target a range of applications.
“Top of our apps list is training and inference; we can do pretty good at graphics for high-end VR/AR … [the architecture] works best for problems with lots of parallelism,” said Ditzel.
The chips will use 16-bit floating point for training but support lower bit widths and integer operations for neural nets, too. “We will have more performance and fewer watts than competitors and more scalable power — most other [training] chips are hot — we can do lower-power apps as well.”
Unlike training accelerators from rivals such as Nvidia, Intel, and startup Graphcore, “we’re not at a max reticle die size,” he said of the 7-nm chip.
One of the company’s early targets may be embedded processors for devices such as Amazon Echo or Google Home. Time-to volume was one lesson from his startup Transmeta, said Ditzel, leading to a strategy of “being able to start in broad consumer spaces rather than day-one in servers” where design cycles can span two years.
The startup’s main business will be selling SoCs; however, it also may sell systems using them. In addition, it is open to licensing its cores “to make RISC-V more widespread.”
The relative immaturity of RISC-V and software for it is a chief challenge today.
“The GCC compiler is pretty stable and Linux ports are being upstreamed, but LLVM still has ways to go,” said Ditzel. “By the time we are selling chips, there will be a lot more maturity. There hasn’t been much silicon until recently with the SiFive parts, but once that’s there, the software will come along.”
“We are in it for the long haul … this is about the next six years, not the next six months.”
Along the way, Esperanto expects to take a lead role in defining extensions to the RISC-V instruction set. The company employs the co-lead of the foundation’s working group on a vector architecture, and Ditzel led work on extensions to Sun’s Sparc CPU back in the day.
For its part, Western Digital plans to transition “future core, processor, and controller development” to RISC-V. It currently consumes more than a billion cores a year. It has been a member of the RISC-V Foundation from the outset but has said little about its plans previously.
“The open-source movement has demonstrated to the world that innovation is maximized with a large community working toward a common goal,” said Martin Fink, WD’s CTO in a press statement.
“For that reason, we are providing all of our RISC-V logic work to the community,” said Fink, who was slated to keynote the event this week. “We also encourage open collaboration among all industry participants, including our customers and partners, to help amplify and accelerate our efforts. Together, we can drive data-focused innovation and ensure that RISC-V becomes the next Linux success story.”
In an FAQ, the company said that it has no plans to make merchant semiconductors. It positioned the move as an extension of its storage business rather than a replacement of it.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times