L4/L5 cars need how much TOPS?
Nvidia insisted that a genuine apples-to-apples comparison on the power efficiency of the two chips can be only made when Xavier and EyeQ5 are compared at 24 TOPS, assuming that both were designed on a 7nm process node.
Based on these parameters (24TOPS at 7nm), Shapiro calculated, “With our current Xavier product, 24TOPS would consume approximately 12W of power for just the DLA (deep learning acceleration) +GPU.” He added, “If we move from the current 16nm to 7nm, we expect power to be reduced by approximately 40 percent, so that would put Xavier at about 7W.”
The Nvidia executive concluded, “Hence the accurate chart would be: at 24 TOPs performance, EyeQ 5 is at 10W and Nvidia Xavier is at 7W.”
Demler doesn’t buy such an argument.
The debate, he said, isn’t about an SoC-to-SoC spec comparison, but the actual performance necessary for L4/L5 autonomous cars. On one hand, “Intel/Mobileye claim their 24 TOPs is sufficient,” said Demler. On the other hand, Nvidia is “building Pegasus [platform] to max out at 320 TOPS.” At issue are, said Demler: “Who has more L4/L5 engagements? How much performance will we need?” Demler said, “Nobody knows, even if Mobileye thinks they do.”
When Nvidia originally announced the Xavier chip, the company quoted 20TOPS at 20W. But now, Nvidia is saying it’s 30TOPS at 30W. What happened?
While acknowledging its originally announced spec, Shapiro explained, “if we cranked the clocks we can scale to 30TOPS at 30W.”
Xavier, described by Nvidia as its “all-new AI supercomputer” in Sept., 2016, is designed for use in self-driving cars. (Source: Nvidia)
Similarly, Intel today seems to quote an EyeQ 5 SoC spec very different from what was originally announced by Mobileye, before it was acquired by Intel.
EyeQ 5, according to Mobileye’s initial announcement, would have processing power of 12 Tera operations per second at power consumption below 5W. But last week when EE Times talked to Jack Weast, Intel's principal engineer and chief architect of autonomous driving solutions, he described EyeQ 5 delivering 24TOPS at 10W.
Asked when and how the SoC’s performance suddenly doubled, an Intel spokeswoman told us that Intel is now planning to deliver multiple EyeQ 5’s, “including the 12TOPs SKU announced previously and the 24TOPS SKU we compared to the Nvidia Xavier product.”
The block diagram of EyeQ 5 when Mobileye announced it in May, 2016 (Source: Mobileye)
Pressed to explain if this means there are two cores integrated inside EyeQ5 24TOPS, or that Intel is using two chips inside a system, the Intel spokeswoman declined to elaborate. She said, “I can’t comment on how we came up with that level of TOPS yet. We’ll have more details on architecture and platform going into CES.”
Meanwhile, Demler was told by Mobileye that “to support Level 4/5, they will use two EyeQ 5s.”
The analyst community is in agreement that the target of Mobileye-designed EyeQ 5 performance is too low compared to Nvidia’s Xavier. Demler described the two EyeQ5’s as “just the ‘eyes’ of the system.” In Intel’s upcoming platform, the brains will come from Atom SoCs.
“EyeQ has relatively weak old MIPS CPUs compared to Nvidia’s custom ARMv8 CPUs (eight of them in Xavier),” noted Demler. “Those custom ARM cores deliver very powerful ‘brains,’ so you don’t need an Atom or Xeon. Therefore, Intel shouldn’t deny that its ‘PC’ processors come into play.”
Next page: Power efficiency