SAN JOSE (ChipWire) -- Taking another step to distinguish itself from Intel Corp., Advanced Micro Devices Inc. today disclosed an internally developed 64-bit microprocessor architecture and complementary bus design.
Once a manufacturer of cloned Intel chips, AMD is moving to position itself as a true alternative supplier to Intel. AMD will debut its "X86-64" architecture today at the Microprocessor Forum in San Jose, along with its Lightning Data Transport (LDT) I/O architecture. AMD executives also said they're considering a so-called K6-2 Plus chip: a K6-2 processor with integrated cache produced in the company's new 0.18-micron process technology. The K6-2 Plus would complement the Athlon Ultra workstation/server chip that AMD plans to ship next year, the company said.
AMD's first 64-bit chip, called Sledgehammer, is expected to ship in 2001, company executives said.
AMD has emerged as the standard-bearer for the x86 instruction set developed by Intel. But Intel's 64-bit architecture requires a completely new infrastructure.
For AMD's X86-64, "the key here is that it's a simple change," said Stephen Lapinski, director of product marketing at AMD's Computation Products Group in Sunnyvale, Calif.
Following years of catastrophic manufacturing flubs, AMD has set out to ensure that the manufacture of the new chip will be the easiest piece of the puzzle. Adding 64-bit capabilities increases the 104-sq.-mm die size of a 32-bit Athlon processor produced in 0.18-micron technology by only 5%, Lapinski said. While AMD's timetable still calls for 0.18-micron manufacturing to begin at Fab 30 in Dresden, Germany in the fourth quarter, the company this week showcased a 700-MHz Athlon running on the new process (see Oct. 4 story).
More importantly, AMD claims that the combination of a small die size and its 0.18-micron process will allow the company to pack more than one 64-bit x86 microprocessor on a single die. That's important, given the fact that x86 integer instruction performance is closing in on RISC chips, Lapinski said. Through triple-operand, double-precision floating-point instructions that AMD is designing for the new architecture, the company hopes to eliminate the floating-point advantage of RISC chips as well, he said.
Other advanced chips maintain some level of x86 compatibility. Intel's Merced microprocessor contains an x86 instruction unit, in addition to the 64-bit architecture. Compaq Computer Corp.'s 64-bit Alpha uses FX!32 binary translations and emulations to translate x86 code into its own native instructions, while Sun Microsystems Inc. pairs an x86 and Sparc core on a single add-on card. But in each case, x86 instructions are relegated to second-class status, Lapinski said.
When pairing more than one microprocessor on a single chip, AMD will use undisclosed custom logic to manage the infrastructure. Off-chip, however, AMD has designed the custom LDT bus for I/O and coprocessor chips. The LDT is a bidirectional bus, either 8, 16, or 32 bits wide (the bit width is negotiable at the device's initialization). Data passes through multiple logic channels in up to eight links or bridges, which can be connected to several daisy-chained devices. Lapinski declined to discuss AMD's coprocessor strategy.
Lapinski also said he realized that there was far more to the 64-bit issue than simply designing a winning chip. "One thing we haven't brought up is the software infrastructure," he said, noting that Microsoft Corp. and Compaq have crossed swords over Windows NT support for Compaq's 64-bit Alpha microprocessor. "We don't think [OS support] will be a problem," he said.
AMD executives thought minimizing the infrastructure changes would be of benefit to OEMs. "Intel took the Merced design and forced it on [the OEMs]," said Bob Mitton, division marketing manager for AMD's workstation products.
Intel executives see things a bit differently. "The bottom line is we have full x86 compatibility," said Ron Curry, director of marketing for IA-64 products at Intel in Santa Clara, Calif. He compared AMD's approach to souping up a Volkswagen with wider tires and a faster engine.
AMD also disclosed further details of its 32-bit microprocessor strategy. Next year, the Athlon Ultra for workstations and servers will feature 1 and 2 megabytes of off-chip, full-speed, 16-way, set-associative Level 2 cache. While AMD executives declined to discuss clock speeds, Lapinski did say that the EV-6 processor bus will run at 266 MHz, or faster than the 200-MHz bus employed by conventional Athlon chips. Related chip sets will feature 66-MHz, 64-bit PCI with 4X AGP Pro connections and a PC 2100 DDR DRAM interface.
Lapinski also said AMD is evaluating the so-called K6-2 Plus, a 0.18-micron K6-2 reported to include 128 or 256 kilobytes of on-chip cache. A third chip without Level 2 cache is also thought to be under consideration, although Lapinski would not divulge details. "When the K6 hits 0.18 micron, there's a couple of things that make sense," he said. "There's a possibility that we'll have more to tell you about what's coming down the pike in the fourth quarter," he said, implying that the news might come at the Fall Comdex trade show in Las Vegas.