SAN FRANCISCO The field of organized initiatives pursuing alternatives to the Intel-backed Rambus DRAM has shrunk by one. A decision by the SLDRAM Inc. consortium to wrap up its own work and throw its support behind the emerging DDR II spec cleaves the DRAM industry into two major camps, amassed along the boundary between desktop and server: the Rambus approach, initially aimed at desktop PCs, and the server-bound double-data-rate SDRAM.
At this week's International Solid-State Circuits Conference here, a paper described a 72-Mbit SLDRAM prototype with a bandwidth of 800 Mbytes/second-half that claimed by Direct Rambus DRAM. The proof-of-concept device was designed by engineers at Mosaid Technologies Inc. (Kanata, Ont.) and fabricated at Siemens Corp.
Some of the concepts developed within the SLDRAM consortium could be adopted by the DDR II group, said Richard Foss, chairman of Mosaid. The concepts include the digitally calibrated delay-locked loop (DLL) and the center-terminated interface, in which the voltage is said to "swing about the middle between the reference voltage and the termination."
The remnants of the SLDRAM consortium also could play a role in the rollout of DDR technology. Rather than disband completely, the SLDRAM consortium will be renamed and will take on a new role, said Desi Rhoden, chairman of Jedec, which is overseeing development of the DDR II specification. Rhoden said he will serve as chairman of the SLDRAM group until its role is redefined and a new name agreed upon that reflects its new purpose. Farhad Tabrizi, a Hyundai Electronics USA marketing executive, relinquished the presidency in December.
The SLDRAM consortium owns a pool of patents and thus "can never die" as a legal entity, said Mosaid's Foss, who estimated that the group spent $4 million to develop its prototype. Micron Technology, impatient with the design-by-committee approach, developed an SLDRAM independently and is in the manufacturing stage now.
Meanwhile, about 60 companies, including computer makers as well as DRAM and module vendors, are behind the DDR II movement, which is expected to complete a formal description of its specification in April. The goal is to have 256-Mbit DDR II samples, operating at 266 MHz, ready by the end of 2000.
The SLDRAM consortium pursued what it originally called the Synclink DRAM with the intention of competing with Rambus. But the group's members-including Fujitsu, Hitachi, Hyundai Electronics, IBM, LG Semicon, Matsushita Electric, Micron Technology, Mitsubishi Electric, NEC, Oki Electric, Samsung Electronics, Siemens, Texas Instruments, Toshiba and Vanguard-voted at a December meeting in Japan to wrap up the SLDRAM chip-development work they had undertaken a year earlier. Now that a proof-of-concept prototype has been achieved, the organization is refocusing.
The SLDRAM effort entered the fray relatively late, and, partly because of its committee-bound structure, never caught up with Rambus Inc., which emerged a decade ago as a tightly focused startup backed by venture capital. When the SLDRAM consortium started its design work in December 1997, Intel was set to announce that it would move to the Rambus architecture after the PC100 technology petered out.
By reading bits from the rising and falling edges of the clock, a DDR II DRAM could become the PC533 specification-a somewhat tongue-in-cheek moniker derived from Intel's PC100 SDRAM specification, which is now in widespread use.
"Some of the technology developed within the SLDRAM consortium, such as the approach to clocking, could be funneled into the DDR II effort," said Steven Przybylski, principal consultant at the Verdande Group (San Jose, Calif.). "The DDR II people are trying to find a combination of technology and cost that will allow them to coexist with Rambus, to develop DDR technology that is better-suited to the server arena and larger systems."
Bob Montoye, a researcher at IBM Corp.'s facility in Yorktown Heights, N.Y., said servers and laptop computers have a common need to minimize power consumption. Both the large boxes-with their many Gbytes of main memory-and the laptops have heat-dissipation issues that DDR II could address.
Montoye said the DDR II specification will deliver "ultra-high bandwidth while in cache mode" and that by adopting a point-to-point architecture rather than a bus-oriented approach, significant power saving could be achieved.
Howard Kalter, a consultant who recently retired from IBM's Vermont memory-development operation, noted that packet-protocol architectures, such as those on which Rambus is based, are not favored among server manufacturers.
A DDR II task group has been formed within Jedec and is in operation now. Several sources said the task group is intent on avoiding the problems that Jedec faced with the initial synchronous-DRAM specification, which was too loosely defined. That had created an opportunity for Intel to step in with its PC66 program to enforce tighter standards.
While the normal Jedec subcommittee will operate in the case of DDR II, Przybylski said, an ad-hoc committee is expected to keep a tight reign on the specification.
For the initial DDR standard-now coming to market at 166-MHz and faster speed grades-a "group of 14" has been named that will police and promote DDR DRAM adoption within the wider industry.
At the ISSCC here this week, DDR SDRAMs at the 1-Gbit density were introduced by three companies. The papers, from IBM, NEC, and Samsung Electronics, all presented variations on the DDR theme.
And in an indication that not all the Rambus licensees will move in lockstep with similar designs, Toshiba Corp. presented a Rambus design that uses a new redundancy scheme-fuses that take up less die area than the previous redundancy approach-and a power-saving refresh scheme that promises to make the RDRAMs suitable for portable applications.
The IBM 1-Gbit DDR prototype measures 390 mm2 on a 0.175-micron process and achieves 800-Mbyte/s operation with a x16 configuration and 1.6 Gbytes/s with a x32 configuration, dissipating 300 mA at 200-MHz DDR operation.
Samsung engineer Hongil Yoon described a gigabit-density DDR design that operates at 2.5 V and achieves a data rate of 333 Mbits/s. Using a 0.14-micron process, the die size is about 349 mm2. In an indication that chip and package are becoming more intimately linked, Samsung developed a flip-chip package that melds with the silicon via copper traces, which act as a form of global routing. Samsung used the ODIC (outer DQ, or data out, and inner control) configuration, which puts the control circuitry in the middle of the die, surrounded by the 16 memory array banks.