Run-time analysis algorithms that decide when and how to adjust a CPU's core clock frequency and core voltage are akin to an automatic transmission for an electronic device: shifting speeds on the fly so as to achieve an optimal combination of increased performance and reduced energy consumption. With the growing ranks of CPUs that feature dynamic adjustment of frequency and voltage, device designers are now looking to clock and voltage scaling as an important weapon in their arsenal of power-reducing design techniques. Designers know that power consumption is directly proportional to frequency and proportional to the square of voltage. As a result, a linear reduction of clock and voltage levels leads to a nonlinear reduction in power usage. But, since a lowered frequency also can lower computational efficiency, the challenge for these designers is to implement clock- and voltage-scaling schemes that do not appreciably alter the run-time performance of the device.
The stakes are fairly high. No matter whether a device uses batteries, fuel cells or solar cells, extended usable life means more freedom and lower costs for the end user, and this can translate into increased device sales. Additionally, environmental issues associated with battery disposal potentially can be mitigated with better power-management schemes.
This challenge in clock and voltage scaling is not to be underestimated. The latest personal digital assistants and cell phones are quite advanced, featuring peripheral-rich hardware platforms, complex multithreading operating systems and myriad application software packages. While modern handheld devices possess a large number of variables that can be analyzed in the adjustment of core clock frequency and core voltage, most of these variables are not used in the interests of reducing algorithm complexity.
The traditional approaches to clock management range from simple to elaborate. On the simpler side, many notebook computers provide controls to adjust frequency based on the power source, the remaining battery life or the CPU's temperature.
Sophisticated approaches, such as "just-in-time" algorithms, dynamically adjust frequency and voltage to maximize the amount of time that the CPU spends executing tasks. The goal of these algorithms is to complete tasks in as long a time as is acceptable, minimizing the amount of time that the CPU is idling.
These techniques are beneficial, but a significant question remains: Can battery life be further extended through additional judicious applications of clock and voltage scaling? In looking beyond raw CPU computational bandwidth, we see that the answer is yes, under certain conditions.
Global clock-management algorithms that take into account all the nuances of device performance and run-time variables can better use frequency and voltage adjustments to extend battery life. An instructive example is the results of experiments on performance and battery life for an HP-Compaq iPaq Pocket PC device with InHand Electronics' BatterySmart power-management software installed. In this experiment, the iPaq continuously stores data files to an ATA flash card peripheral, and the graph on page 55 shows performance and battery life measurements at four different frequency values.
When clock frequency is decreased from 206 MHz to 81 MHz, data throughput to the peripheral decreases less than 5 percent. Yet, battery life increases by more than 30 percent, with the reduced frequency. Why? Because data throughput is fairly independent of the CPU's clock frequency. Instead, the performance bottleneck is related to the CPU's electronic interface with the peripheral and the internal makeup of the peripheral itself.
The future goal-the so-called holy grail of clock and voltage scaling for designers striving to eke out that last increment of battery life-is an adjustment algorithm that takes into account all the relevant degrees of freedom in the hardware and software of an electronic device. The algorithm would analyze these degrees of freedom and isolate a core clock frequency and core voltage adjustment signal, just as an automobile's automatic transmission shifts gears to provide speed, performance and fuel economy. The resulting algorithm could be implemented in system software, a FPGA, an ASIC, an advanced voltage regulator or the CPU itself.