Steven Kawamoto, Sr. Marketing Manager, Custom LSI Solutions Unit, Gaku Ogura, Sr. Marketing Manager, Design Solutions Center, Richard Lee, Design Engineer, Design Solutions Center, NEC Electronics America, Inc., Santa Clara, Calif.
The integration of test capabilities into the underlying structure of an ASIC eliminates the extra design-for-test (DFT) steps that complicate conventional front- and back-end design flows. Rather than distracting from the primary design goals, this DFT approach takes no extra time. In fact, overall design and production turnaround time decreases along with costs because robust DFT structures can be integrated with significantly less effort than with a standard ASIC. Additionally, the layout of the DFT structures does not interfere with the chip's other functions.
The key to this type of ASIC is its use of embedded intellectual property (IP) combined with an array of logic elements that you can use as needed. The embedded IP can include DFT structures such as boundary scan, internal scan, built-in self-testing (BIST) and IP testing as well as circuitry to minimize clock skew and signal-integrity issues. This IP can take advantage of the same process technology used in cell-based ASICs. Moreover, the embedded IP can be highly optimized outside of the time pressures that drive the typical design cycle. Such IP therefore utilizes the silicon area efficiently and provides a platform on which you can build customized system-on-chip functions.
An important aspect of this type of ASIC platform involves the way the various metal layers are used. In a process that has five metal layers, for example, the bottom three layers may be used to integrate the embedded IP while the top two metal layers interconnect the user-configured logic elements an array of logic building blocks whose characteristics help define a new type of ASIC.
In NEC Electronics' Instant Silicon Solution Platforms (ISSPs), for example, the logic elements consist of more complex building blocks than you would find in traditional gate arrays, but they are more fine-grained than the building blocks in field-programmable gate arrays (FPGAs). In the ISSP array, the basic building block is a module comprising a combinational block and a simple sequential block.
The goal in this type of configuration is to minimize ASIC turnaround time while maximizing performance. As shown in this article, the platform array approach has profound implications for several design and verification steps, including DFT.
Before looking at the way the pre-integrated DFT structures affect the design flow, consider the types of DFT structures that are appropriate for a platform array. Note that the DFT goal is to ensure testability for production testing (for determining whether the chip was manufactured correctly). DFT is not for functional testing; determining whether the chip was designed correctly is a task for the customer's design verification tools.
The high-level DFT objective is to reduce the testing costs of complex chips. A key requirement in meeting this objective is to increase the accessibility of the chip's internal nodes. In general, you have to be able to establish a specific signal value at any node in the circuit by controlling inputs and observing outputs.
Properly implemented, a combination of DFT techniques can achieve testability close to 100 percent and will not interfere with the chip's normal functions. NEC Electronics believes that boundary scan, internal scan, memory BISTs and an internal IP test are all worthwhile ways to meet testability goals.
Boundary-scan circuitry complies with the IEEE-1149.1 Test Access Port (TAP Controller) and Boundary-Scan Standard, also referred to as JTAG. The boundary-scan function has a couple of modes, but the most useful for chips is probably the external testing mode. This mode enables a testing methodology for interface buffers that checks I/O reliability for a chip mounted on a board. Without this capability, it is difficult to determine whether all the I/Os in high-density packages such as ball grid arrays are making proper contact with the board.
Internal-scan circuitry adds the capability to control and observe the testing of internal nodes by shifting the data in and out through the internal-scan chain. The more scan chains you have, the faster you can apply test vectors and get results. This technique is useful for complex chips because shifting data in and out of a large design via a single-scan chain can take a long time.
BIST for RAM
To implement the BIST function, you need to embed the capability to apply test vectors to the chip's internal IP and then evaluate the test results. In a chip such as a platform array, a BIST is especially useful for testing embedded RAM. Because RAM structures are uniform, a small set of test vectors can provide excellent fault coverage. Having a large number of embedded RAM blocks is important in platform arrays because the RAM can serve so many purposes. For a small BIST investment, you get a good payoff in terms of ensuring the reliability of these crucial components. In contrast, if you rely on external RAM testing, you waste enormous amounts of time moving test data on and off the chip.
The NEC Electronics TestBus is another DFT structure that allows efficient access to IP cores or commodity megafunctions while minimizing the use of additional testing pins. TestBus complies with IEEE P1500. For IP core testing, a control scan path (CSP) chain connecting each IP block to be tested is created. The CSP chain is terminated at the TAP controller. And the TAP controller determines which macro will be tested in this CSP chain. Once the macro to be tested is determined, test data is applied to the macro test pins.
When implementing DFT structures in a conventional ASIC, you have to consider technical trade-offs such as die area, I/O pins and performance, as well as economic issues such as design and test generation time and yield. The platform array minimizes or eliminates all of these concerns except for the use of test-oriented I/O pins, which are minimized by the use of JTAG and TestBus circuits.
Pre-integrating the test structures results in a highly optimized design that keeps performance and die area/yield trade-offs to an absolute minimum. The pre-integrated structures eliminate the time penalties associated with DFT in front-end design, back-end design and production, and almost completely eliminate the time needed for test generation.
Designers think of platform array technology as a way to save fabrication time, but this type of ASIC is equally effective at saving design time including DFT and verification time. The design flow for platform arrays requires fewer steps than a typical cell-based flow and the steps that you avoid save a significant amount of time.
Chief among the unnecessary steps is DFT, with its additional synthesis and verification burden. Platform arrays also have no need of steps such as power routing and clock tree synthesis because these resources are integrated into the platform's basic structure. With global clocks ranging upward of 250 MHz, pre-optimizing the clock trees eliminates both clock skew issues and signal-integrity concerns. In fact, you avoid any signal-integrity issues (such as crosstalk, antenna effects and IR drop) in all of the IP that is pre-integrated into the platform. Since that IP may range from SRAM and analog phase-locked loops to multigigabit-per-second serial interfaces and 32-bit embedded processors, the time savings can be significant. Signal-integrity analysis is necessary only for the customized metal layers usually only two layers in a five- or six-layer chip.
While the platform approach eliminates some design/verification steps, the steps that you do need are the same basic steps used for a typical cell-based ASIC synthesis followed by logic verification using static timing analysis (STA) or an at-speed function test if you cannot verify the design using STA. After back-end design by the ASIC vendor, you verify timing based on the back-annotated delay information.
Note that the customizable portion of platform arrays can implement the same IP megacells contained in some cell-based libraries. In addition to saving initial design time, this capability allows you to take advantage of the platform's two-week engineering sample fabrication turn and then rapidly convert to a cell-based ASIC to get an efficient area-optimized design for high-volume applications.
All too often, designers have ignored proven design-for-test methodologies, choosing instead to save the time and cost associated with acquiring DFT tools, designing DFT structures and developing the associated test vectors. Platform array-based ASICs solve this dilemma with pre-integrated DFT capabilities that add no extra time or cost. These ASICs thus save time in design and verification as well as fabrication compared with cell-based ASICs, while offering significant speed, power and cost advantages over FPGAs.
Chung Ho, director, Custom LSI Solutions Unit at NEC Electronics, also contributed to this article.
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