MONTEREY, Calif. IBM believes it will be first. Intel will start before the end of the year. Texas Instruments will start early next year. Others will follow. Leading chip makers are working to move 90-nanometer process technologies into volume production, and several are already offering samples of 90-nm designs. But the hurdles of 90-nm design and production are still significant, according to a panel of industry executives convened last week.
The panel, chaired by EE Times senior editor Ron Wilson, enumerated many pitfalls of ultradeep-submicron design and manufacture.
When pressed, two panelists Ted Vucurevich, senior vice president of Cadence Design Systems Inc., and Antun Domic, senior vice president and general manager of nanometer operations at Synopsys Inc. agreed that 90-nm designs would start ramping next year. Vucurevich said it would come in the form of an FPGA, while Domic said it would be a "non-FPGA" design, drawing chuckles.
The panel, aside from the light-hearted jousting over timing, did split over the treacheries ahead in the 90-nm shift.
"The hurdles to getting to lower cost seem much different at 90 nm" than for previous generational transitions, Vucurevich said. For instance, developing an advanced system-on-chip device is put at $25 million and a year's design time vs. a typical ASIC design that costs from $300,000 to $500,000, he said.
In addition, the costs of packaging a 90-nm design could be more expensive than the silicon itself, Vucurevich said. "You're going to have to find new ways of verifying your design," he said.
But Domic countered that he believed the shift from 180-nm to 130-nm designs was far more difficult than the transition to 90 nm will be. In the earlier transition, the electronics industry had to deal with the introduction of copper as a wiring choice and new dielectrics to handle the tighter geometries.
"Getting yields on that proved harder than expected," he said.
Andrew Moore, design services marketing manager with foundry Taiwan Semiconductor Manufacturing Co. Ltd., chimed in that the tools issues are dif-ferent this time around. "The things at 130 nm that were nice to have are must-haves at 90 nm," he said, noting that modeling of gate currents and SRAM redundancy contingency plans are imperative.
"There is a great deal of concern over variables," said Tim Burks, vice president of product development at Magma Design Automation Inc. "People are definitely concerned about low yields."
Vucurevich said manufacturing issues are increasingly global in that, for instance, designers need to fret about clock skew over multiple interconnects. But over time, local issues will also weigh heavy on manufacturing.
"Think globally and fear locally, then," Wilson quipped.