SAN JOSE, Calif. After years of work and a thumbs-up from NASA, researchers at the University of Idaho have designed a chip whose power consumption is more than an order of magnitude less than that in existing satellite chips.
Using a modified 0.35-micron CMOS process and some fancy circuit techniques, the team has developed a radiation-hardened Reed-Solomon error-correction chip for spacecraft that operates from just 500 millivolts. For those keeping track of the industry's International Technology Roadmap for Semiconductors, that's about eight years ahead of schedule.
Early samples of the chip have already been fabricated, tested and validated by NASA. Barring any schedule changes, the chips are headed for space next year as part of the agency's Nanosat, or New Millennium ST5, mission, which will place miniature spacecraft weighing less than 50 pounds into orbit around the Earth.
Powered by solar energy, the minisatellites are made to orbit the globe in clusters, measuring charged particles in the magnetosphere. Only about the size of a 21-inch TV, they are designed to do many of the same tasks as their larger counterparts, and include sophisticated guidance, altitude-control and communications systems.
One of their jobs will be to send a steady stream of scientific and operation data back to Earth. To that end, the Reed-Solomon chip will encode the data so that any errors that occur during transmission can be detected and corrected on the ground. The encoder is active about 10 percent of the time, which is considered a high rate of activity by VLSI standards, said Jody Gambles, associate director of the Center for Advanced Microelectronics and Biomolecular Research at the University of Idaho.
The chip was designed so that the operating voltage could be lowered to the point where static power and active power are equal. In this way, power can be cut with minimal impact on performance.
Normally, static power is much lower than active power, but the design team wanted to keep the threshold voltages low in order to maintain good performance. By making adjustments to the doping levels and tweaking the transistor design, threshold levels were set near or below 0 V for n-channel transistors and slightly positive for p-channel devices. Operating voltages are adjusted using the transistor body effect by controlling the back-bias voltage of the substrate and the well, according to a paper the team presented at the recent Custom Integrated Circuits Conference here.
"We knew we wanted to operate at 500 mV, given the 10 percent activity factor. From there, you can figure out how you are going to balance the dynamic and static power," Gambles said.
Running at 60 MHz, the ultralow-power device consumes 14.3 milliwatts, about 30 times less power than an earlier 3.3-V design. The optimum frequency, where total power and static power are about the same, is at 47 MHz.
Gambles said the technology is best-suited for active logic circuits but not memory. "The technology shines when signals are being switched," he said. "The encoder is a nice example. It's sitting in the telemetry chain of the spacecraft doing error correction and it's nearly continuous."
A big challenge was finding a manufacturing partner that would give the university access to its process technology and let it make changes. Eventually the center teamed with AMI Semiconductor Inc. (Pocatello, Idaho). The center has licensed its technology to PicoDyne Inc. (Annapolis, Md.), which is handling product delivery of the Reed-Solomon chip for NASA.