TOKYO Although structured ASICs are helping designers shorten turn-around time and lower NRE costs for system-on-chip LSIs, ASSPs will emerge as the long-term solution for a wider range of core silicon, according to an analyst for iSuppli Japan.
In a keynote speech at the Electronic Design Solution Fair 2005.in Yokohama earlier this week, Yoshihisa Toyosaki, president of iSuppli Japan, told the audience, "The advantage of the structured ASIC is limited."
Toyosaki added that the Japanese semiconductor industry, seeking to capitalize on the digital consumer electronics craze, will discover that their business model based on custom chips is not feasible in a market marked by strong price competition and short product life cycles. ASSPs will be required to be competitive in such a market, he said, acknowledging that the largest ASSP suppliers are outside Japan.
The structured ASIC offers advantages where its cost is equal or less than that of PLD and cell-based ICs. The range of applications where ASICs are advantageous is not wide, estimated iSuppli.
In many cases, manufacturers are shifting from ASICs to ASSPs for volume products. For example, while high-end digital cameras still use custom ASICs, higher volume, lower cost cameras are built with ASSPs.
While vendors expect the structured ASIC market to reach $250 million in 2007, iSuppli offered three scenarios. The most favorable projectd much larger growth, reaching $376 million in 2007. In the middle is a projection that tracks vendors' expectations. The worst case projects that the market will grow to less than half the level to $117 million. Though iSuppli endorses the most favorable scenario in its forecast for the structured ASICs,
Toyosaki called the worst-caase scenario the most probable.
Realizing the limitations of ASICS, at least one Japanese chip vendor has developed an alternate approach.
Toshiba Corp. exhibited Universal Array, a system-on-chip design platform for 130 nm and beyond. The Universal Array platform is designed to cut turn-around-time significantly, while maintaining the high density integration and low power consumption of cell based ICs.
Toshiba claims the Universal Array platform halves the time between the completion of design and the availability of engineering samples. With cell based-ICs, the tape out timing is after layout design and timing verification. On the Universal Array platform, diffusion wafer fabrication starts at the completion of prototyping. Layout design and timing verification occurs in parallel to the diffusion wafer process.
Toshiba intends to offer engineering samples of its 130nm generation TC280 cell-based IC series the first quarter of 2005. The 90nm TC300 series will follow in the second quarter.
ICs based on the Universal Array platform offer similar chip size and performance to cell-based ICs and can use all IP for those parts, according to a Toshiba spokesman.
But proponents of structured ASICs maintain that by embedding basic functions and by limiting the number of customized interconnect layers, the technology offers shorter turnaround time and lower cost compared to cell-based ICs.
Synplicity K.K., the Japan unit of Synplicity, Inc. demonstrated a structured ASIC with three semi-custom ASIC vendors--Fujitsu Ltd., LSI Logic and NEC Electronics Corp.
NEC offers ISSP (Instant Silicon Solution Platform) and LSI Logic brought RapidChip in 2002. Fujitsu followed with AccelArray in 2003. The structure and customizable interconnection layers differ between vendors.