Santa Cruz, Calif. Reducing leakage current is a well-known design challenge at 90 nanometers and below. But leakage is also a design-for-manufacturability problem that has become a source of design-related yield loss, some industry observers say.
Handel Jones, CEO of International Business Strategies Inc., came to the recent Fabless Semiconductor Association Expo with a harsh warning. In a panel presentation, he said that DFM factors have slowed the ramp-up to 90-nm wafer volumes and threaten to delay 65 nm even further. And, Jones said, leakage is the major reason for DFM yield loss.
While some industry insiders see leakage as a potential culprit in yield loss, most wouldn't say it's the primary factor. Others see leakage as a design issue, not a yield problem. No one disagrees that the problem is severe at 90 nm and worse at 65 nm.
"Assuming you have defect density under control, as major companies pretty much have, leakage is the largest contributor to yield losses," Jones said. "The industry is not really 'fessing up to the problem. It was starting to be acknowledged, but I think it's being swept under the rug again at 65 nm."
Because of DFM factors, Jones said, the ramp-up to 90-nm-production wafers has taken more than two years and the ramp-up to 65 nm may take nearly three, compared with 1.5 years for 130 nm.
Whether one sees leakage as a yield problem depends somewhat on how one defines yield. Jones identified three types of yield loss those that are process-related, reticle-related and design-related. The latter category is the one that's growing fastest, and it's primarily caused by leakage, Jones said. At 65 nm, design-related yield loss can reduce overall yields by 30 percent, he said.
The industry traditionally thinks in terms of random-defect-related yield, noted Marc Levitt, DFM platform vice president at Cadence Design Systems Inc. But if you start to consider parametric yield basically what Jones would call design-related then leakage and power issues become very important, he said.
"You might do a functional test and find that 70 percent of your dice are good," Levitt said. "Then you do a leakage test and find you're above a certain number of milliamps, and suddenly that 70 percent drops to 35 percent. So you could have a 35 percent yield loss because of leakage." In other words, if you have to throw a chip into the trash because it consumes too much power, it didn't yield.
Leakage can also cause hot spots in a design and perhaps even thermal runaway. In extreme cases, said Nitin Deo, vice president of marketing at DFM startup Ponte Solutions Inc., it can lead to catastrophic failures such as dislocation-
induced leakage between the source and drain of a transistor. "Leakage is one of the major sources of parametric failure," Deo said. "It is underestimated today. Designers do not have an understanding of leakage as a source of yield loss they see it only as a performance/power factor."
Synopsys Inc. makes a distinction between random and systematic yield, with the latter referring to things that are systematically happening. "Leakage has become a key driver of that [systematic] segment of the yield-loss mechanism," said Anantha Sethuraman, vice president of DFM for the silicon engineering group.