Foundries have mixed views. Taiwan Semiconductor Manufacturing Co. Ltd. views leakage as a design rather than a yield issue, a spokesman said. But TSMC has made leakage reduction a primary goal of its recently introduced 65-nm reference flow. United Microelectronics Corp. thinks differently. "Yield loss caused by leakage is contributed by the higher power consumption, which may impact the design performance through a rise in temperature," said Suzanna Chang, senior director of marketing at UMC.
Gary Smith, chief EDA analyst at Gartner Dataquest, doesn't think leakage will cause yield loss unless it's detected through Iddq testing. But leakage can show up in power or timing failures caused by regional heating, he noted.
"Power-limited yield loss is a reality," said Andrew Kahng, founder and chairman of startup Blaze DFM Inc. "Typically, such bad parts are detected using Iddq testing." Kahng added that systematic, parametric yield loss will start to eclipse random defects at future process nodes.
An insidious problem
With the reduction in voltage thresholds and with thinner gate oxides, leakage problems are beginning to increase exponentially. Leakage may be responsible for 50 percent of a chip's power consumption at 90 nm, and perhaps as much as 80 percent at 65 nm. According to Jones' studies, both subthreshold and gate-oxide leakage are growing far faster than dynamic power, although high-k materials may slow gate-oxide leakage somewhat.
Leakage is also extremely susceptible to process, temperature and voltage variations. It is strongly interdependent with temperature, and just as leakage can cause hot spots, thermal gradients can cause huge increases in leakage. Critical-dimension variations can also wreak havoc with leakage.
Leakage variation can be as much as fivefold, said Robert Hoogenstryd, director of marketing implementation at Synopsys. "If your chip is consuming five times as much leakage current as expected, the chip will run hotter and maybe eventually melt, or not perform because of temperature inversion," he said.
Fortunately, things can be done to reduce leakage, such as swapping in high-voltage-threshold cells where performance is not critical. For this reason, many 90- and 65-nm processes provide low-Vt and high-Vt libraries. Designers can also set up voltage islands and power down sections of the chip that aren't in use.
TSMC's 65-nm reference flow offers power-gating technology based on multithreshold CMOS, letting users insert high-Vt footers to shut down circuits that are not operating. Intel Corp. claims its recently introduced its P1265 process reduces transistor leakage 1,000 times over its high-performance 65-nm process. The trade-off is that transistor performance is lower by a factor of two. IBM and Texas Instruments have also introduced 65-nm processes that claim dramatically lower leakage.
Both resolution enhancement technology and lithography simulation can also help, said Blaze DFM's Kahng. But more needs to be done. "We will see future tools that reduce leakage and improve power-limited yield while being aware of both design and process constraints," he said.