SAN FRANCISCO, Calif. When representatives of some of the world's largest EDA users gathered at a panel discussion at the Design Automation Conference here Tuesday (July 25), talk often turned to the impact of process variability. But concerns over design costs, chip density, and power management were also high on the list.
The panel, titled "the IC nanometer race," included representatives from STMicroelectronics, Intel, Texas Instruments, Samsung, and TSMC. Moderator Wally Rhines, chairman and CEO of Mentor Graphics, launched the panel by asking each participant to describe the most important issue facing the electronics industry.
"My biggest concern at the 65-, 45- and 32-nm process nodes is variability," said Ho-Kyu Kang, vice president at Samsung Electronics. "Critical design rules have been scaled by 30 percent every other year, but variability has not scaled by the same rule. So variability becomes bigger and bigger as design rules scale."
STMicroelectronics foresees a "discontinuity" with respect to the design tool solutions needed at 45 nm and beyond, said Philippe Magarshack, vice president of central CAD at STMicroelectronics. "We're dealing with restricted design rules on the one hand, and on the other looking for any way we can predict system variability and account for it in design, rather than with design margins."
At advanced process nodes, Magarshack added, analog and RF design becomes more challenging, lower device voltages raise power concerns, and complexity grows. What's needed, he said, is to mitigate the complexity of design by assembling an "ecosystem" including system-level design, hardware/software co-verification, and virtual prototyping.
According to Dennis Buss, vice president for silicon technology development at Texas Instruments, the biggest challenge facing the industry today is the high cost of custom designs. With design costs around $50 million, he said, "low volume ASICs will become a thing of the past." The cost is impacted dramatically, he said, by power management needs, parametric variation, and system-on-chip integration including analog components.
"What I see in the future is the co-development of architecture, design, and process technology," Buss said. Keeping process development separate, he said, doesn't work given today's need to manage power, variability and analog/RF integration.
Gadi Singer, vice president and general manager of Intel's low power IA and technologies group, outlined four major nanometer design challenges. One is increasing density, leading to a huge logic capacity; another is increasing complexity, with technologies such as multiple power domains. A third challenge, the convergence of computing and communications, creates low power demands. The fourth challenge is time to market.
There are four "dimensions" EDA vendors must take to attack these problems, Singer said. One is "up" to higher levels of abstraction, another is "sideways" with full platforms, another is "down" with design for manufacturing (DFM), and a fourth dimension is "time," with faster turnaround times for design.
Things really aren't so bad, said Fu-Chieh Hsu, vice president for design and technology platforms at TSMC. "Issues like power, design costs, and integration can all be successfully addressed if we continue collaborative partnerships with manufacturers, customers, IP [intellectual property] and EDA providers," he said.
Despite the challenges, panel participants said they're ramping up now on 65 nm designs, and will be prototyping 45 nm designs later this year or next year.