SAN FRANCISCO, Calif. The right combination of better modeling and regular IC fabrics could be the best way to resolve IC variability challenges, according to panelists at the Design Automation Conference here Wednesday (July 26). That message emerged as representatives of major EDA user companies were asked to place bets on hypothetical startup companies.
Panel moderator Bill Joyner, director of computer-aided design and test at the Semiconductor Research Corp. (SRC), presented 8 hypothetical companies with potential solutions for nanometer variability, and asked panelists where they'd invest. The winners were startups offering lithography and process variation modeling, variation-resistant regular fabrics, and variation-tolerant design. Companies pursuing extraction, placement, routing, and yield optimization gained less support.
Clive Bittlestone, fellow and physical verification manager at Texas Instruments, noted that simple corner analysis with margins is becoming a struggle. "That keeps me awake at night," he said. "It's a key shift." Most design for manufacturing (DFM) effects are served by available tools, but "true" variability analysis and optimization is still needed, he said.
Bittlestone showed a list of design concerns at various process nodes. His top concerns at 65 nm are gate shape, design rule checking (DRC), models, statistical timing analysis, and placement and routing; critical area analysis (CAA), stress, and extraction ranked low. Restricted design rules (RDRs) may reduce the need for DFM, he said, but DFM will still be needed.
Transistors are getting "fat," said Sani Nasssif, manager of tools and technology at IBM's Austin Research Laboratory, because with optical proximity correction (OPC) the number of shapes that determine the final outcome increases. No longer can designers assemble transistors and not care how they interact, he said. "CAD built on composability is gone," Nassif said. "It's a major change in how we do design."
Vijay Pitchumani, project engineer at Intel, had three suggestions for coping with variability. One is to minimize variability through "robust" design rules and layout policies. The second is to model deterministic variations first. This would include most device, interconnect, voltage and temperature variations, he said. The third suggestion is to invent cost-effective, variation-tolerant designs.
The variability problem, said Riko Radojcic, design-to-silicon initiative director at Qualcomm Technologies, is really an "accounting" problem. "Process corners are too wide," he said. "We put all sorts of variation into one set of corners."