SAN FRANCISCO Synopsys Inc. said Wednesday (July 26) it has donated a library of SystemVerilog assertion checkers, defined in the ARM-Synopsys Verification Methodology Manual (VMM) for SystemVerilog, to EDA standards organization Accellera.
The checkers, provided as SystemVerilog source code, have been used by design and verification engineers for the past few years to add SystemVerilog assertions (SVA) to their designs, according to
Synopsys (Mountain View, Calif.).
The donated library contains 20 unique assertion checkers, complementary to Accellera's current OVL of assertion monitors, Synopsys said.
"We are certainly in favor of assertion checkers, as they help SoC [system-on-chip] designers to complete their verification work more quickly," said Mike Turpin, chair of Accellera's OVL technical subcommittee and principal validation engineer at ARM. "Synopsys' donation of these additional checkers to become part of the OVL industry-standard library is to be applauded."
Accellera's OVL technical committee solicited user input at a Design Automation Conference (DAC) meeting here Wednesday.